Systems and methods for reducing high order hall plate sensitivity temperature coefficients
The systems and methods described can reduce high order temperature coefficients on the Hall plate sensitivity. A temperature coefficient circuit may include a first amplifier to receive a first reference voltage generated in conjunction with a proportional to absolute temperature (PTAT) device and a second amplifier to receive a second reference voltage generated in conjunction with a complementary to absolute temperature (CTAT) device, the second amplifier having a second output node. A plurality of resistors may be disposed in a signal path between output node of the first amplifier and an output node of the second amplifier. The plurality of resistors may be coupled to at least one voltage-to-current converter through one or more resistors taps. The voltage-to-current converter may generate at least one current signal that can be operable to apply a multiplication factor or a division divisor to an amplifier coupled to the voltage-to-current converter.
1. A circuit comprising:
a first amplifier to receive a first reference voltage generated in conjunction with a proportional to absolute temperature (PTAT) device, the first amplifier having a first output node;
a second amplifier to receive a second reference voltage generated in conjunction with a complementary to absolute temperature (CTAT) device, the second amplifier having a second output node;
a plurality of resistors disposed in a signal path between the first output node and the second output node, the plurality of resistors having at least one resistor tap;
at least one voltage-to-current converter coupled to the at least one resistor tap, the at least one voltage-to-current converter to generate a respective at least one current signal; and
a third amplifier, the third amplifier coupled to the at least one current signal, the at least one current signal operable to apply a multiplication factor or a division divisor to the third amplifier.
2. The circuit of claims 1 , wherein the at least one resistor tap comprises a plurality of resistor taps, wherein the at least one voltage-to-current converter comprises a plurality of voltage-to-current converters, wherein the circuit further comprises:
a multiplexer coupled between the plurality of resistors and the plurality of voltage-to-current converters, the multiplexer having a plurality of input nodes coupled to the plurality of resistor taps, the plurality of multiplexers having a plurality of output nodes, wherein the multiplexer receives one or more voltages from the plurality of resistor taps and generates a multiplication reference voltage related to the multiplication factor and a division reference voltage related to the division divisor.
3. The circuit of claim 1 , wherein the first reference voltage is coupled to a noninverting terminal of the first amplifier.
4. The circuit of claim 1 , wherein the second reference voltage is coupled to a noninverting terminal of the second amplifier.
5. The circuit of claim 2 , wherein the multiplexer comprises:
a first multiplexer having one or more input nodes coupled to the plurality of resistors; and
a second multiplexer having one or more inputs coupled to the plurality of resistors;
wherein the first multiplexer receives one or more voltages from the plurality of resistors and generates the multiplication reference voltage and the second multiplexer receives one or more voltages from the plurality of resistors and generates the division reference voltage.
6. The circuit of claim 2 , further comprising a first converter coupled to the multiplexer, wherein the first converter receives the multiplication reference voltage and generates a multiplication reference current.
7. The circuit of claim 1 , wherein the first reference voltage has a predetermined non-zero sensitivity to temperature.
8. The circuit of claim 1 , wherein the first and second amplifiers comprise respective noninverting operational amplifiers.
9. A circuit comprising:
a first amplifier to receive a first reference voltage generated in conjunction with a first device, the first amplifier having a first output node;
a second amplifier to receive a second reference voltage generated in conjunction with a second device, the second amplifier having a second output node;
a plurality of resistors disposed in a signal path between the first output node and the second output node, the plurality of resistors having at least one resistor tap;
at least one voltage-to-current converter coupled to the at least one resistor tap, the at least one voltage-to-current converter to generate a respective at least one current signal; and
a third amplifier, the third amplifier coupled to the at least one current signal, the at least one current signal operable to apply a multiplication factor or a division divisor to the third amplifier.
10. The circuit of claim 9 , wherein the first device is a proportional to absolute temperature (PTAT) device.
11. The circuit of claim 9 , wherein the second device is a complementary to absolute temperature (CTAT) device.
12. The circuit of claim 9 , wherein the at least one resistor tap comprises a plurality of resistor taps, wherein the at least one voltage-to-current converter comprises a plurality of voltage-to-current converters, wherein the circuit further comprises:
a multiplexer coupled between the plurality of resistors and the plurality of voltage-to-current converters, the multiplexer having a plurality of input nodes coupled to the plurality of resistor taps, the plurality of multiplexers having a plurality of output nodes, wherein the multiplexer receives one or more voltages from the plurality of resistor taps and generates a multiplication reference voltage related to the multiplication factor and a division reference voltage related to the division divisor.
13. The circuit of claim 9 , wherein the first reference voltage is coupled to a noninverting terminal of the first amplifier.
14. The circuit of claim 9 , wherein the second reference voltage is coupled to a noninverting terminal of the second amplifier.
15. The circuit of claim 12 , wherein the multiplexer comprises:
a first multiplexer having one or more input nodes coupled to the plurality of resistors; and
a second multiplexer having one or more inputs coupled to the plurality of resistors;
wherein the first multiplexer receives one or more voltages from the plurality of resistors and generates the multiplication reference voltage and the second multiplexer receives one or more voltages from the plurality of resistors and generates the division reference voltage.
16. The circuit of claim 12 , further comprising a first converter coupled to the multiplexer, wherein the first converter receives the multiplication reference voltage and generates a multiplication reference current.
17. The circuit of claim 9 , wherein the first reference voltage has a predetermined non-zero sensitivity to temperature.
18. The circuit of claim 9 , wherein the first and second amplifiers comprise respective noninverting operational amplifiers.
19. A circuit comprising
a first amplifier to receive a first reference voltage generated in conjunction with a first device, the first amplifier having a first output node;
a second amplifier to receive a second reference voltage generated in conjunction with a second device, the second amplifier having a second output node;
a plurality of resistors disposed in a signal path between the first output node and the second output node, the plurality of resistors having at least one resistor tap; and
at least one voltage-to-current converter coupled to the at least one resistor tap, the at least one voltage-to-current converter to generate a respective at least one current signal.
20. The circuit of claim 19 ,
wherein the at least one current signal is operable to apply a multiplication factor or a division divisor.