IP Library Granted Patent US 12,455,301
Granted Patent B2
US 12,455,301 · App. 18/535,157 · Granted Oct 28, 2025

Hall plate current sensor having stress compensation

Inventors: Roman Procházka (Struharov, CZ); Juan Manuel Cesaretti (Buenos Aires, AR)
Assignee: Allegro MicroSystems, LLC
G01R15/202
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Quick Facts
Patent No.
US 12,455,301
App. No.
18/535,157
Granted
Oct 28, 2025
Kind
B2
Abstract

Methods and apparatus for a voltage driven Hall plate current sensor integrated circuit (IC) package that includes a die including a Hall plate with a lateral epi resistor. A gm amplifier receives an output voltage from the Hall plate and a front end amplifier receives an output of the gm amplifier. A compensation circuit compensates for stress on the die that affects a resistance of the Hall plate and includes a lateral epi resistor coupled to a constant current for compensating for piezoresistive stress in the Hall plate.

Claims (41)

1. A voltage driven Hall plate current sensor integrated circuit (IC) package, comprising:

a die including a Hall plate comprising a Hall lateral epi resistor;

a gm amplifier to receive an output voltage from the Hall plate;

a front end amplifier to receive an output of the gm amplifier;

compensation circuit to compensate for stress on the die that affects a resistance of the Hall plate, the compensation circuit including a compensation lateral epi resistor coupled to a temperature-dependent current for compensating for piezoresistive stress in the Hall plate, wherein the compensation lateral epi resistor is coupled to the gm amplifier;

a bandgap circuit to generate the temperature-dependent current for the compensation lateral epi resistor; and

a vertical epi resistor coupled to a variable current source corresponding to a temperature sensitivity value, wherein the vertical epi resistor is configured to compensate for piezo stress sensitivity of the Hall plate.

2. The IC package according to claim 1 , wherein the gm amplifier comprises a Gilbert cell.

3. The IC package according to claim 2 , further including a degeneration resistor coupled to terminals of the Gilbert cell.

4. The IC package according to claim 1 , further including a digital-to-analog converter (DAC) to receive and output the temperature sensitivity value.

5. The IC package according to claim 4 , wherein the DAC is coupled to a temperature dependent current.

6. The IC package according to claim 1 , wherein the vertical epi resistor is coupled to the gm amplifier.

7. The IC package according to claim 1 , further including a back end amplifier coupled to an output of the front end amplifier.

8. A method, comprising:

employing a die including a Hall plate comprising a Hall lateral epi resistor, wherein the die forms a part of a voltage driven Hall plate current sensor integrated circuit (IC) package;

connecting a gm amplifier to receive an output voltage from the Hall plate;

connecting a front end amplifier to receive an output of the gm amplifier;

configuring a compensation circuit to compensate for stress on the die that affects a resistance of the Hall plate, wherein the compensation circuit includes a compensation lateral epi resistor coupled to a first temperature dependent current source for compensating for piezoresistive stress in the Hall plate, wherein the compensation lateral epi resistor is coupled to the gm amplifier;

configuring a bandgap circuit to generate the first temperature dependent current source for the compensation lateral epi resistor; and

coupling a vertical epi resistor to a second temperature dependent current source corresponding to a temperature sensitivity value, wherein the vertical epi resistor is configured to compensate for piezo stress sensitivity of the Hall plate.

9. The method according to claim 8 , wherein the gm amplifier comprises a Gilbert cell.

10. The method according to claim 9 , further including a degeneration resistor coupled to terminals of the Gilbert cell.

11. The method according to claim 8 , further including connecting a digital-to-analog converter (DAC) to receive and output the temperature sensitivity value.

12. The method according to claim 11 , wherein the DAC is coupled to a third temperature dependent current.

13. The method according to claim 8 , wherein the vertical epi resistor is coupled to the gm amplifier.

14. The method according to claim 8 , further including connecting a back end amplifier coupled to an output of the front end amplifier.

15. A voltage driven Hall plate current sensor integrated circuit (IC) package, comprising:

a die including a Hall plate comprising a lateral epi resistor;

a Gilbert cell including a gm amplifier having inputs to receive a differential output voltage from the Hall plate, a degeneration resistor coupled to terminals of the gm amplifier;

a front end amplifier to receive an output of the gm amplifier, wherein first and second feedback resistor are coupled in a feedback configuration for first and second inputs of the front end amplifier;

a compensation circuit comprising:

a lateral epi resistor RCONST coupled to the gm amplifier via a second current generator active device and to a temperature dependent current ICONST for compensating for piezoresistive stress in the Hall plate;

a vertical epi resistor RVAR coupled to the gm amplifier via a first current generator active device and to a DAC configured to receive a temperature sensitivity value;

a first reference resistor connected to the first current generator active device via a first amplifier and configured to receive a bandgap temperature dependent current from a bandgap circuit; and

a first reference resistor connected to the DAC and to a current source configured to provide a DAC temperature dependent current, wherein an output of the DAC is coupled to the vertical epi resistor RVAR via a first amplifier.

16. The IC package according to claim 15 , wherein the first and second reference resistors are matched for a same temperature.

17. The IC package according to claim 15 , wherein the degeneration resistor and the first and second feedback resistors are a same type.

18. The IC package according to claim 15 , wherein the degeneration resistor and the first and second feedback resistors are matched to achieve a same temperature.

19. The IC package according to claim 15 , further including a bandgap circuit to provide the temperature dependent current to the DAC.

20. The IC package according to claim 15 , wherein a temperature coefficient of the Gilbert cell is trimmed using a constant k Iptat_denom for coarse signal path trimming.

21. The IC package according to claim 20 , wherein the temperature coefficient of the Gilbert cell is finely trimmed by the temperature sensitivity value at the input of the DAC.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2023
From: PROCHÁZKA, ROMAN; CESARETTI, JUAN MANUEL; ALLEGRO MICROSYSTEMS ARGENTINA S.A.
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 065840/0815 →
Continuity (1)
Related Publication 20250189562A1 · Jun 12, 2025
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