Logic compatible RRAM structure and process

1. A device comprising:

a first dielectric layer disposed over a substrate, the first dielectric layer including a first portion spaced apart from a second portion such that a first region extends from the first portion to the second portion of the first dielectric layer;

a first electrode disposed within the first region and extending to over the first portion of the first dielectric layer such that the first electrode extends laterally over the first portion of the first dielectric layer by a first distance beyond the first region;

a resistive layer disposed within the first region over the first electrode and extending to over the first portion of the first dielectric layer;

a second electrode including a first portion disposed over the resistive layer within the first region and a second portion extending over the first portion of the first dielectric layer; and

a second dielectric layer that includes a first portion disposed over the first portion of the second electrode and a second portion disposed over the second portion of the second electrode, the first portion of the second dielectric layer being closer to the substrate than the second portion of the second dielectric layer.

2. The device of claim 1 , wherein the resistive layer extends laterally over the first portion of the first dielectric layer by the first distance beyond the first region, and

wherein the second electrode extends laterally over the first portion of the first dielectric layer by a second distance beyond the first region, the second distance being less than the first distance.

3. The device of claim 2 , wherein the second dielectric layer extends laterally over the first portion of the first dielectric layer by the second distance beyond the first region.

4. The device of claim 1 , further comprising a conductive via extending from the second electrode and wherein the conductive via physically contacts the first portion of the second dielectric layer.

5. The device of claim 1 , wherein the first electrode further extends laterally over the second portion of the first dielectric layer by a second distance beyond the first region, and

wherein the second electrode extends laterally over the second portion of the first dielectric layer by a third distance beyond the first region, the third distance being less than the second distance.

6. The device of claim 1 , further comprising a spacer structure disposed directly on a sidewall of the second portion of the second dielectric layer and on a sidewall of the second electrode.

7. The device of claim 6 , wherein the spacer structure physically contacts a top surface of the resistive layer, the top surface of the resistive layer facing away from the substrate.

8. A device comprising:

a conductive feature disposed in a substrate;

a first dielectric layer disposed over the substrate;

a first electrode including a first portion disposed directly on the conductive feature and a second portion disposed over the first dielectric layer, the first portion of the first electrode being at a first height and the second portion of the first electrode being at a second height that is different from the first height;

a resistive layer including a first portion disposed over the first portion of the first electrode and a second portion disposed over the second portion of the first electrode;

a second electrode including a first portion disposed over the first portion of the resistive layer and a second portion disposed over the second portion of the resistive layer, the first portion of the second electrode being at a third height and the second portion of the second electrode being at a fourth height that is different from the third height and the second height; and

a spacer feature extending along a sidewall of the second portion of the second electrode to the resistive layer.

9. The device of claim 8 , further comprising a second dielectric layer including a first portion disposed over the first portion of the second electrode and a second portion disposed over the second portion of the second electrode, the first portion of the second dielectric layer being at a fifth height and the second portion of the second dielectric layer being at a sixth height that is different from the fifth height, fourth height, third height, second height and the first height.

10. The device of claim 9 , further comprising:

a third dielectric layer disposed over the second dielectric layer; and

a via extending through the third dielectric layer and the second dielectric layer to the second electrode.

11. The device of claim 10 , wherein the third dielectric layer extends continually from the via to the spacer feature.

12. The device of claim 8 , wherein the substrate includes a dielectric material, and

wherein the conductive feature includes a metal line.

13. The device of claim 8 , wherein the first electrode extends laterally over the substrate by a first distance; and

wherein the second electrode extends laterally over the substrate by a second distance beyond the first distance of the first electrode.

14. The device of claim 8 , wherein the resistive layer includes a material selected from the group consisting of NiO, TiO, HfO, ZrO, ZnO, WO 3 , Al 2 O 3 , TaO, MoO, and CuO.

15. A method comprising:

forming a first material layer over a substrate;

forming a first electrode layer over the first material layer;

forming a resistive layer over the first electrode layer;

forming a second electrode layer over the resistive layer;

patterning the second electrode layer, wherein the patterned second electrode layer extends laterally over the substrate by a first distance; and

patterning the resistive layer and the first electrode layer such that a portion of at least one of the patterned resistive layer and the patterned first electrode layer extends laterally over the substrate by a second distance beyond the first distance of the patterned second electrode layer.

16. The method of claim 15 , wherein the patterned first electrode layer includes a first portion and a second portion, the first portion of the patterned first electrode layer is at a first height and the second portion of the patterned first electrode layer is at a second height that is different from the first height; and

wherein the patterned second electrode layer includes a first portion and second portion, the first portion of the patterned second electrode layer is at a third height and the second portion of the patterned second electrode layer is at a fourth height that is different from the third height and the second height.

17. The method of claim 15 , further comprising forming a spacer feature along a sidewall of the patterned second electrode layer prior to patterning the resistive layer and the first electrode layer.

18. The method of claim 15 , further comprising forming a second material layer over the second electrode layer, and

wherein patterning the second electrode layer further includes patterning the second material layer.

19. The method of claim 18 , further comprising:

forming a dielectric material layer over the patterned second electrode layer;

forming a trench through the dielectric material layer; and

forming a conductive feature in the trench.

20. The method of claim 15 , wherein the substrate includes a conductive feature, and

wherein forming the first electrode layer over the first material layer includes forming the first electrode layer directly on the conductive feature.