Metal gate and manufacturing method thereof
The present disclosure provides a semiconductor structure, including an active region with a first surface; an isolated region having a second surface, surrounding the active region, the first surface being higher than the second surface; and a metal gate having a plurality of metal layers disposed over the first surface and the second surface. A ratio of a thinnest portion and a thickest portion of at least one of the plurality of metal layers is greater than about 40%.
1. A semiconductor structure, comprising:
an active region with a first surface;
an isolated region having a first top surface surrounding the active region, the first surface being higher than the first top surface;
a dielectric layer disposed over the first surface and an entirety of the first top surface of the isolated region;
a masking layer over a second top surface of the isolated region and in contact with the metal gate, the second top surface being higher than the first top surface; and
a metal gate having a plurality of metal layers, the plurality of metal layers disposed over the dielectric layer,
wherein a ratio of a thinnest portion and a thickest portion of at least one of the plurality of metal layers is greater than about 40%.
2. The semiconductor structure of claim 1 , wherein the at least one of the plurality of metal layers is a work function metal layer.
3. The semiconductor structure of claim 1 , wherein the thickest portion is over the first surface.
4. The semiconductor structure of claim 3 , wherein the thinnest portion is at a corner connecting the first surface and the first top surface.
5. The semiconductor structure of claim 1 , wherein the metal gate comprises Al metal layer.
6. The semiconductor structure of claim 1 , further comprising a high k dielectric layer between the metal gate and the active region.
7. The semiconductor structure of claim 1 , a height difference between the first surface and the first top surface being in a range of from about 9 nm to about 11 nm.
8. A field effect transistor (FET), comprising:
an active region surrounded by an isolated region, a sidewall and a first surface of the active region protruding from a second surface of the isolated region;
a dielectric layer disposed over the first surface and an entirety of the second surface of the isolated region;
a metal gate at least covering the sidewall and the first surface of the active region, and
a masking layer over a third surface of the isolated region and in contact with the metal gate, the third surface being higher than the second surface;
wherein an Al-containing layer of the metal gate comprises:
a first thickness in proximity to the first surface of the active region; and
a second thickness in proximity to a corner connecting the first surface and the sidewall of the active region, and
a thickness ratio of the second thickness and the first thickness is greater than about 40%.
9. The FET of claim 8 , wherein the FET is an N-type FET.
10. The FET of claim 8 , wherein the Al-containing layer comprises TiAl.
11. The FET of claim 8 , further comprising a TiN layer between the Al-containing layer and the active region.
12. The FET of claim 8 , wherein the second thickness is in a range of from about 1.5 nm to about 2 nm.
13. The FET of claim 8 , wherein a length of the metal gate is substantially a length of the first surface, and a width of the metal gate is about 20 nm.
14. A semiconductor structure, comprising:
an active region with a first surface;
an isolated region having a second surface, surrounding the active region, the first surface being higher than the second surface;
a dielectric layer disposed over the first surface and an entirety of the second surface of the isolated region; and
a metal gate having a plurality of metal layers disposed over the dielectric layer, and
a masking layer over a third surface of the isolated region and in contact with the metal gate, the third surface being higher than the second surface,
wherein a ratio of a thinnest portion and a thickest portion of an aluminum barrier layer is greater than about 40%, the thickest portion being measured at the first surface, and the thinnest portion being measured at a corner connecting the first surface and the second surface.
15. The semiconductor structure of claim 14 , further comprising a TiN layer between the aluminum barrier layer and the active region.
16. The semiconductor structure of claim 14 , wherein the dielectric layer comprises a high k dielectric layer between the metal gate and the active region.
17. The semiconductor structure of claim 14 , wherein the aluminum barrier layer comprises TiAl.
18. The semiconductor structure of claim 14 , wherein the thinnest portion of the aluminum barrier layer is in a range of from about 1.5 nm to about 2 nm.
19. The semiconductor structure of claim 14 , wherein the semiconductor structure is an N-type FET.
20. The semiconductor structure of claim 14 , wherein a width of the metal gate is about 20 nm.