Silicon intermixing layer for blocking diffusion
A method of forming an integrated circuit structure includes forming a gate dielectric on a wafer, forming a work function layer over the gate dielectric, depositing a capping layer over the work function layer, soaking the capping layer in a silicon-containing gas to form a silicon-containing layer, forming a blocking layer after the silicon-containing layer is formed, and forming a metal-filling region over the blocking layer.
1. A method comprising:
forming a gate stack comprising:
forming a gate dielectric over a semiconductor region of a wafer;
forming a work-function layer over the gate dielectric;
depositing a first capping layer comprising titanium nitride over the work-function layer, wherein the depositing the first capping layer is performed starting with a composite cycle comprising:
a first TiCl 4 pulsing-and-purging cycle; and
a NH 3 pulsing-and-purging cycle following the first TiCl 4 pulsing-and-purging cycle, wherein the depositing the first capping layer is ended with a second TiCl 4 pulsing-and-purging cycle;
forming a silicon-containing layer over and physically contacting the first capping layer;
after the silicon-containing layer is formed, performing a vacuum break to expose the silicon-containing layer to air and to form a silicon-and-oxygen-containing layer, wherein the silicon-and-oxygen-containing layer is configured for charges to tunnel through; and
forming a metallic material over the silicon-and-oxygen-containing layer.
2. The method of claim 1 , wherein the forming the silicon-containing layer comprises soaking the wafer in a silicon-containing gas.
3. The method of claim 2 , wherein the soaking the wafer in the silicon-containing gas is performed when the wafer is heated.
4. The method of claim 3 , wherein in the soaking the first capping layer, the wafer is heated to a temperature in a range between about 400° C. and about 600° C.
5. The method of claim 2 , wherein the forming the work-function layer, the depositing the first capping layer, and the forming the silicon-containing layer are performed in a vacuum chamber, and wherein the method further comprises, after the wafer is soaked in the silicon-containing gas, performing a vacuum break.
6. The method of claim 1 , wherein the second TiCl 4 pulsing-and-purging cycle is performed at an elevated wafer temperature, and is free from plasma.
7. The method of claim 1 , wherein the depositing the first capping layer further comprises a plurality of additional composite cycles following the composite cycle, and wherein a TiCl 4 pulsing duration in the second TiCl 4 pulsing-and-purging cycle is longer than TiCl 4 pulsing durations during the composite cycle and the plurality of additional composite cycles.
8. The method of claim 1 further comprising, depositing a second capping layer comprising titanium nitride over and contacting the silicon-containing layer, wherein the metallic material is formed over the second capping layer.
9. The method of claim 8 , wherein the depositing the second capping layer and the forming the silicon-containing layer are performed in a same process chamber.
10. A method comprising:
forming a gate stack on a semiconductor region, the forming the gate stack comprising:
depositing a first titanium nitride layer over the semiconductor region, wherein the depositing the first titanium nitride layer is performed starting with a first TiCl 4 pulsing-and-purging cycle, followed by a NH 3 pulsing-and-purging cycle, and wherein the depositing the first titanium nitride layer is ended with a second TiCl 4 pulsing-and-purging cycle;
forming a silicon-containing layer over the first titanium nitride layer;
performing a vacuum break to expose the silicon-containing layer to air and to form a silicon oxide layer, wherein the silicon oxide layer is configured for charges to tunnel through;
depositing a second titanium nitride layer over the silicon oxide layer; and
depositing a metal-filling region over the second titanium nitride layer.
11. The method of claim 10 , wherein the depositing the first titanium nitride layer comprises a plurality of additional TiCl 4 pulsing-and-purging cycles between the first TiCl 4 pulsing-and-purging cycle and the second TiCl 4 pulsing-and-purging cycle.
12. The method of claim 11 , wherein a first TiCl 4 pulsing duration in each of the first TiCl 4 pulsing-and-purging cycle and the plurality of additional TiCl 4 pulsing-and-purging cycles is shorter than a second TiCl 4 pulsing duration in the second TiCl 4 pulsing-and-purging cycle.
13. The method of claim 10 , wherein the silicon-containing layer is formed through a soaking process.
14. The method of claim 13 further comprising forming a work-function layer, wherein the first titanium nitride layer is deposited over the work-function layer, and wherein in the soaking process, the first titanium nitride layer is exposed to a silicon-containing gas.
15. The method of claim 14 , wherein the silicon-containing gas is selected from the group consisting of SiH 4 , Si 2 H 6 , Dichlorosilane (DCS), and combinations thereof.
16. A method comprising:
forming a gate stack comprising:
forming a gate dielectric on a semiconductor region;
forming a work-function layer over the gate dielectric;
depositing a first titanium nitride layer over the work-function layer, wherein the depositing the first titanium nitride layer is performed starting with a first titanium chloride pulsing-and-purging cycle, followed by an ammonia pulsing-and-purging cycle, and wherein the depositing the first titanium nitride layer is ended with a second titanium chloride pulsing-and-purging cycle;
forming a silicon-containing layer over and contacting the first titanium nitride layer;
performing a vacuum break to expose the silicon-containing layer to air; and
forming a metal-filling region over the silicon-containing layer that has been exposed to air.
17. The method of claim 16 , wherein a first titanium chloride pulsing process in the first titanium chloride pulsing-and-purging cycle lasts for a first duration, and a second titanium chloride pulsing process in the second titanium chloride pulsing-and-purging cycle lasts for a second duration longer than the first duration.
18. The method of claim 17 , wherein a ratio of the second duration to the first duration is in a range between about 2 and about 5.
19. The method of claim 16 further comprising depositing a second titanium nitride layer over and contacting the silicon-containing layer.
20. The method of claim 16 , wherein the gate stack is comprised in a Fin Field-Effect Transistor (FinFET).