Multiple-stacked semiconductor nanowires and source/drain spacers

1. A semiconductor device, comprising:

a substrate;

a plurality of nanowires extending in a first direction on the substrate and arranged in a second direction perpendicular to the first direction, wherein each nanowire is spaced apart from an immediately adjacent nanowire;

a gate structure wrapping around each of the nanowires when viewed in a cross section taken along a longitudinal axis of the gate structure perpendicular to the first and second directions, wherein when viewed in a cross section taken along the first direction, the gate structure has gate portions interleaved with the nanowires;

a source region on one side of the gate structure; and

a plurality of source spacers each extending from a respective one of the gate portions into the source region,

wherein the gate structure has an uneven bottom surface.

2. The semiconductor device of claim 1 , wherein the gate structure comprises a high-k material, and the high-k material wrapping around each of the nanowires when viewed in the cross section taken along the longitudinal axis of the gate structure and is in contact with the source spacers when viewed in the cross section taken along the first direction.

3. The semiconductor device of claim 1 , further comprising a gate spacer extending above a topmost one of the nanowires along a sidewall of the gate structure.

4. The semiconductor device of claim 1 , further comprising an interlayer dielectric layer extending along a top surface of the source region.

5. The semiconductor device of claim 1 , wherein the source region has a plurality of protruding portions interleaved with the source spacers when viewed in the cross section taken along the first direction.

6. The semiconductor device of claim 1 , wherein a bottom surface of the gate structure is lower than a bottom surface of the source region.

7. A semiconductor device comprising:

nanowires extending in a first direction on a substrate and arranged in a second direction perpendicular to the first direction, wherein each nanowire is spaced-apart from an immediately, adjacent nanowire;

a gate structure wrapping around each of the nanowires when viewed in a cross section taken along a longitudinal axis of the gate structure perpendicular to the first and second directions, wherein when viewed in a cross section taken along the first direction, the gate structure has lower gate portions interleaved with the nanowires and an upper gate portion extending above a topmost one of the nanowires, and the lower gate portions comprise a gate dielectric layer and a work function metal layer and the upper gate portion comprises the gate dielectric layer, the work function metal layer, and a gate electrode extending over the nanowires but not between the nanowires;

a source region on one side of the gate structure;

a first gate spacer extending along a first sidewall of the upper gate portion facing toward the source region; and

a source spacer extending from the first sidewall of the upper gate portion into a position in the source region.

8. The semiconductor device of claim 7 , wherein the source spacer is in contact with the gate dielectric layer of the gate structure.

9. The semiconductor device of claim 7 , wherein the source spacer has a sidewall coterminous with a sidewall of the first gate spacer.

10. The semiconductor device of claim 7 , wherein the source spacer comprises a germanium-containing oxide.

11. The semiconductor device of claim 7 , further comprising

a second gate spacer extending along a second sidewall of the gate structure, wherein a bottom portion of the second gate spacer is lower than a bottom portion of the first gate spacer.

12. A semiconductor device comprising:

a fin structure over a substrate;

nanowires formed over the fin structure;

an isolation structure surrounding the fin structure;

a gate structure formed across the fin structure and wrapping around the nanowires;

a source/drain structure attached to the nanowires;

a first gate spacer formed on a first sidewall of the gate structure; and

source/drain spacers sandwiched between the source/drain structure and the gate structure,

wherein an interface between the source/drain spacers and the fin structure is higher than a top surface of the isolation structure.

13. The semiconductor device of claim 12 , wherein the gate structure comprises:

a gate dielectric layer wrapping around the nanowires;

a work function metal layer formed over the gate dielectric layer; and

a gate electrode formed over the work function metal layer,

wherein spaces between two neighboring nanowires are fully filled with the gate dielectric layer and the work function metal layer.

14. The semiconductor device of claim 12 , further comprising:

a second gate spacer formed on a second sidewall of the gate structu herein the second gate spacer is in direct contact with the isolation structure.

15. The semiconductor device of claim 12 , further comprising:

a second gate spacer formed on a second sidewall of the gate structure, wherein a portion of the gate structure is sandwiched between the second gate spacer and the nanowires.

16. The semiconductor device of claim 12 , further comprising:

a second gate spacer formed on a second sidewall of the gate structure, wherein a portion of the gate structure is sandwiched between the second gate spacer and the source/drain spacers.

17. The semiconductor device of claim 12 , wherein the nanowires have first ends and second ends opposite to the first ends, and the first ends of the nanowires are in direct contact with the source/drain structure, and the second ends of the nanowires are in direct contact with the gate structure.

18. The semiconductor device of claim 12 , wherein the gate structure has an uneven bottom portion.