Integrated circuit structures having backside gate tie-down
Integrated circuit structures having backside gate tie-down are described. In an example, a structure includes a first vertical stack of horizontal nanowires over a first sub-fin, and a second vertical stack of horizontal nanowires over a second sub-fin, the second vertical stack of horizontal nanowires spaced apart from and parallel with the first vertical stack of horizontal nanowires. A gate structure includes a first gate structure portion over the first vertical stack of horizontal nanowires, wherein the first gate structure extends along an entirety of the first sub-fin. A second gate structure portion is over the second vertical stack of horizontal nanowires, wherein the second gate structure does not extend along an entirety of the second sub-fin. A gate cut is between the first gate structure portion and the second gate structure portion.
1. An integrated circuit structure, comprising:
a first vertical stack of horizontal nanowires over a first sub-fin;
a second vertical stack of horizontal nanowires over a second sub-fin, the second vertical stack of horizontal nanowires spaced apart from and parallel with the first vertical stack of horizontal nanowires; and
a gate structure, comprising:
a first gate structure portion over the first vertical stack of horizontal nanowires, wherein the first gate structure extends along an entirety of the first sub-fin;
a second gate structure portion over the second vertical stack of horizontal nanowires, wherein the second gate structure does not extend along an entirety of the second sub-fin; and
a gate cut between the first gate structure portion and the second gate structure portion.
2. The integrated circuit structure of claim 1 , further comprising a backside contact coupled to the first gate structure.
3. The integrated circuit structure of claim 2 , wherein the backside contact extends laterally beneath a portion of the first sub-fin.
4. The integrated circuit structure of claim 1 , further comprising a dielectric gate plug in the gate cut.
5. The integrated circuit structure of claim 4 , wherein the dielectric plug extends into an isolation structure between the first sub-fin and the second sub-fin.
6. An integrated circuit structure, comprising:
a first fin over a first sub-fin;
a second fin over a second sub-fin, the second fin spaced apart from and parallel with the first fin; and
a gate structure, comprising:
a first gate structure portion over the first fin, wherein the first gate structure extends along an entirety of the first sub-fin;
a second gate structure portion over the second fin, wherein the second gate structure does not extend along an entirety of the second sub-fin; and
a gate cut between the first gate structure portion and the second gate structure portion.
7. The integrated circuit structure of claim 6 , further comprising a backside contact coupled to the first gate structure.
8. The integrated circuit structure of claim 7 , wherein the backside contact extends laterally beneath a portion of the first sub-fin.
9. The integrated circuit structure of claim 6 , further comprising a dielectric gate plug in the gate cut.
10. The integrated circuit structure of claim 9 , wherein the dielectric plug extends into an isolation structure between the first sub-fin and the second sub-fin.
11. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first vertical stack of horizontal nanowires over a first sub-fin;
a second vertical stack of horizontal nanowires over a second sub-fin, the second vertical stack of horizontal nanowires spaced apart from and parallel with the first vertical stack of horizontal nanowires; and
a gate structure, comprising:
a first gate structure portion over the first vertical stack of horizontal nanowires, wherein the first gate structure extends along an entirety of the first sub-fin;
a second gate structure portion over the second vertical stack of horizontal nanowires, wherein the second gate structure does not extend along an entirety of the second sub-fin; and
a gate cut between the first gate structure portion and the second gate structure portion.
12. The computing device of claim 11 , further comprising:
a memory coupled to the board.
13. The computing device of claim 11 , further comprising:
a communication chip coupled to the board.
14. The computing device of claim 11 , wherein the component is a packaged integrated circuit die.
15. The computing device of claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
16. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first fin over a first sub-fin;
a second fin over a second sub-fin, the second fin spaced apart from and parallel with the first fin; and
a gate structure, comprising:
a first gate structure portion over the first fin, wherein the first gate structure extends along an entirety of the first sub-fin;
a second gate structure portion over the second fin, wherein the second gate structure does not extend along an entirety of the second sub-fin; and
a gate cut between the first gate structure portion and the second gate structure portion.
17. The computing device of claim 16 , further comprising:
a memory coupled to the board.
18. The computing device of claim 16 , further comprising:
a communication chip coupled to the board.
19. The computing device of claim 16 , wherein the component is a packaged integrated circuit die.
20. The computing device of claim 16 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.