IP Library › Granted Patent US 10,756,216
Granted Patent B2
US 10,756,216 · App. 16/059,101 · Granted Aug 25, 2020

Nanosheet mosfet with isolated source/drain epitaxy and close junction proximity

Inventors: Xin Miao (Guilderland, NY); Alexander Reznicek (Troy, NY); Choonghyun Lee (Rensselaer, NY); Jingyun Zhang (Albany, NY)
Assignee: International Business Machines Corporation
H01L29/7856H01L21/823418H01L21/823431H01L21/823468H01L21/823481H01L23/5329H01L29/0649H01L29/0673H01L29/66545H01L29/66553H01L29/66795H01L29/42356H01L2029/7858
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Quick Facts
Patent No.
US 10,756,216
App. No.
16/059,101
Granted
Aug 25, 2020
Kind
B2
Abstract

A sacrificial inner dielectric spacer is formed on physically exposed sidewalls of each recessed semiconductor channel material nanosheet of a nanosheet material stack that further includes recessed sacrificial semiconductor material nanosheets that have an inner dielectric spacer formed on physically exposed sidewalls thereof. A local isolation region is then formed by selective epitaxial growth on a surface of a semiconductor substrate containing the nanosheet material stack. After forming the local isolation region, the sacrificial inner dielectric spacers are removed and a source/drain region is formed on the physically exposed surface of each recessed semiconductor channel material nanosheet. A portion of the source/drain structure is formed in a gap located between each neighboring pair of vertically spaced apart inner dielectric spacers.

Claims (14)

1. A semiconductor structure comprising:

a plurality of stacked and suspended semiconductor channel nanosheets located above a semiconductor substrate;

a functional gate structure surrounding a portion of each semiconductor channel nanosheet of the plurality of stacked and suspended semiconductor channel nanosheets, wherein a bottommost surface of the functional gate structure that is located beneath a bottommost semiconductor channel nanosheet of the plurality of stacked and suspended semiconductor channel nanosheets directly contacts the semiconductor substrate;

an inner dielectric spacer located on a sidewall of the functional gate structure and present above and beneath each semiconductor channel nanosheet of the plurality of stacked and suspended semiconductor channel nanosheets;

a source/drain (S/D) structure located on each side of the functional gate structure, wherein a portion of the S/D structure physically contacts a sidewall of each of the semiconductor channel nanosheets and is present in a gap located between each neighboring pair of vertically spaced apart inner dielectric spacers; and

a local isolation region present between the source/drain structure and the semiconductor substrate, wherein an entirety of a topmost surface of the local isolation region directly contacts a bottommost surface of the S/D structure, and wherein at least a portion of a sidewall of the local isolation region directly contacts a sidewall of a bottommost inner dielectric spacer that is located beneath the bottommost semiconductor channel nanosheet of the plurality of stacked and suspended semiconductor channel nanosheets.

2. The semiconductor structure of claim 1 , wherein the local isolation region is composed of an epitaxial oxide that is lattice matched to an upper portion of the semiconductor substrate.

3. The semiconductor structure of claim 2 , wherein the epitaxial oxide is composed of lanthanum (II) oxide, gadolinium(III)-oxide, dysprosium(III)-oxide, holmium(III) oxide, erbium (III) oxide, thulium (III) oxide, lutetium(III) oxide, cerium (IV) oxide, lanthanum-yttrium oxide, gadolinium-erbium oxide, neodymium-erbium oxide, neodymium-gadolinium oxide, or lanthanum-erbium oxide.

4. The semiconductor structure of claim 1 , wherein the local isolation region is composed of a semi-insulating wide bandgap semiconductor material.

5. The semiconductor structure of claim 4 , wherein the semi-insulating wide bandgap semiconductor material is composed of chromium doped GaP.

6. The semiconductor structure of claim 1 , wherein the local isolation region is present on a recessed surface of the semiconductor substrate.

7. The semiconductor structure of claim 1 , wherein the plurality of stacked and suspended semiconductor channel nanosheets is located on a pedestal portion of the semiconductor substrate.

8. The semiconductor structure of claim 1 , further comprising an interlayer dielectric material layer on the source/drain structure.

9. The semiconductor structure of claim 8 , further comprising a contact structure contacting a surface of the source/drain structure and embedded in the interlayer dielectric material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 9, 2018
From: MIAO, XIN; REZNICEK, ALEXANDER; LEE, CHOONGHYUN; ZHANG, JINGYUN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 046592/0713 →
Continuity (1)
Related Publication 20200052124A1 · Feb 13, 2020
Cited By (4)
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