IP Library Granted Patent US 10,757,821
Granted Patent B2
US 10,757,821 · App. 16/382,103 · Granted Aug 25, 2020

Single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor

Inventors: Siping Bai (Zhuhai, CN); Xianglan Wu (Zhuhai, CN); Zhijian Wang (Zhuhai, CN); Zhigang Yang (Zhuhai, CN); Jinqiang Zhang (Zhuhai, CN)
Assignee: RICHVIEW ELECTRONICS CO., LTD.
H05K3/429C23C14/48H05K1/115H05K3/42H05K2201/096H05K2203/092
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Quick Facts
Patent No.
US 10,757,821
App. No.
16/382,103
Granted
Aug 25, 2020
Kind
B2
Abstract

A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board ( 10 ) comprises the following steps: drilling a hole on a substrate ( 11 ), the hole comprising a blind hole and/or a through hole (S 1 ); on a surface ( 12 ) of the substrate, forming a photoresist layer having a circuit negative image (S 2 ); forming a conductive seed layer on the surface ( 12 ) of the substrate and a hole wall ( 19 ) of the hole (S 3 ); removing the photoresist layer, and forming a circuit pattern on the surface ( 12 ) of the substrate (S 4 ), wherein Step S 3 comprises implanting a conductive material below the surface ( 12 ) of the substrate and below the hole wall ( 19 ) of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.

Claims (8)

1. A Method for manufacturing multi-layer circuit board, comprising:

implementing laying-up plate and lamination in the order of metal foil, middle sticking layer, single-layer circuit board, middle sticking layer, single-layer circuit board, middle sticking layer, metal foil;

drilling a hole on the multi-layer plate after lamination, the hole comprises through hole and/or blind hole;

forming a conductive seed layer on a hole wall of said hole; and

removing part of said metal foil, to form circuit pattern,

wherein forming a conductive seed layer comprises implanting a conductive material below the hole wall of said hole via ion implantation, to form ion implantation layer as at least part of said conductive seed layer.

2. The method of claim 1 , wherein during said ion implantation, the ions of said conductive material gain energy of 1-1000 keV, are implanted below a hole wall of said hole and/or below the outer surface of said surface sticking layer for a depth of 1-500 nm, and form steady doping structure with said substrate.

3. The method of claim 1 , wherein step forming a conductive seed layer further comprises, depositing a conductive material above said ion implantation layer via plasma deposition, to form plasma deposition layer, said plasma deposition layer and said ion implantation layer constitute said conductive seed layer, wherein during said plasma deposition, the ions of said conductive material gain energy of 1-1000 eV, forms said plasma deposition layer in a thickness of 1-10000 nm.

Assignments (2)
CHANGE OF NAME Recorded Aug 6, 2025
From: RICHVIEW ELECTRONICS CO., LTD.
To: THINKTRANS ELECTRONIC MATERIALS (SHENZHEN) CO., LTD.
Reel/Frame 072361/0575 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2020
From: BAI, SIPING; WU, XIANGLAN; WANG, ZHIJIAN; YANG, ZHIGANG; ZHANG, JINQIANG
To: RICHVIEW ELECTRONICS CO., LTD.
Reel/Frame 052284/0687 →
Priority Claims (1)
CN 2015 1 0747884 · Nov 6, 2015 · national
Continuity (2)
Division 15773772
Related Publication 20190239363A1 · Aug 1, 2019