IP Library › Granted Patent US 10,763,252
Granted Patent B2
US 10,763,252 · App. 15/883,537 · Granted Sep 1, 2020

Semiconductor device

Inventors: Akio Yamano (Matsumoto, JP); Misaki Takahashi (Matsumoto, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H01L27/0664H01L27/0727H01L29/0638H01L29/0696H01L29/0834H01L29/1095H01L29/36H01L29/407H01L29/7397H01L29/8613H01L29/45
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,763,252
App. No.
15/883,537
Granted
Sep 1, 2020
Kind
B2
Abstract

A semiconductor device including a semiconductor substrate and a plurality of trench structures formed on the semiconductor substrate. The semiconductor substrate includes a first element region for forming an insulated gate bipolar transistor therein, and a second element region for forming a diode therein, the semiconductor substrate constituting a drift layer. The plurality of trench structures includes a plurality of gate trench structures provided on a front surface side of the first element region, each gate trench structure having an electrode provided therein that is based on a gate potential, and a plurality of floating trench structures provided on a front surface side of the second element region, each floating trench structure having an electrode provided therein that has a floating potential.

Claims (33)

1. A semiconductor device, comprising:

a semiconductor substrate including

a first element region for forming an insulated gate bipolar transistor therein, and

a second element region for forming a diode therein,

the semiconductor substrate constituting a drift layer; and

a plurality of trench structures formed on the semiconductor substrate, including

a plurality of gate trench structures provided on a front surface side of the first element region, each gate trench structure having an electrode provided therein that is based on a gate potential,

a plurality of emitter trench structures provided on the front surface side of the first element region, each emitter trench structure having an electrode provided therein that is based on an emitter potential, and

a plurality of floating trench structures provided at least on a front surface side of the second element region, each floating trench structure having an electrode provided therein that has a floating potential, the floating trench structures being larger in number in the second element region than in the first element region, wherein

the plurality of floating trench structures are provided on the second element region only, and

the plurality of emitter trench structures are not provided on the second element region.

2. The semiconductor device according to claim 1 , wherein each of the trench structures includes

a trench,

an insulating film provided in the trench, and

the electrode provided on the insulating film.

3. The semiconductor device according to claim 1 , wherein the plurality of emitter trench structures are provided also on the front surface side of the second element region.

4. The semiconductor device according to claim 3 , further comprising:

an interlayer insulating film provided on the plurality of trench structures in the first and second element regions, and

an emitter electrode provided on the interlayer insulating film, wherein

the interlayer insulating film includes a plurality of contact holes,

end portions of the emitter trench structures are connected with the emitter electrode via the contact holes, and

the floating trench structures are insulated from the emitter electrode by the interlayer insulating film.

5. The semiconductor device according to claim 3 , further comprising:

a collector electrode on a rear surface of the semiconductor substrate, wherein

a gate capacitance CdsT between the emitter trench structures and the floating trench structures, and the collector electrode satisfies CdsT/CdsT 0 ≤3/4, where CdsT 0 is the gate capacitance in a case where only the first element region is provided in the semiconductor device and only the emitter trench structures are formed in the first element region.

6. The semiconductor device according to claim 3 , wherein the floating trench structures are provided also in the first element region.

7. The semiconductor device according to claim 1 , wherein

the semiconductor substrate is of a first conductivity type; and

the semiconductor device further includes, in the first element region,

a base region of a second conductivity type provided between adjacent ones of the trench structures in the first element region, and

an emitter region of the first conductivity type provided on the base region.

8. The semiconductor device according to claim 1 , wherein

the plurality of floating trench structures are not provided on the first element region and are provided on the second element region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2018
From: YAMANO, AKIO; TAKAHASHI, MISAKI
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 044771/0025 →
Priority Claims (1)
JP 2017-050653 · Mar 15, 2017 · national
Continuity (1)
Related Publication 20180269202A1 · Sep 20, 2018
Cited By (1)
US 12,224,316