CHIP package
An integrated fan-out package including an integrated circuit, a plurality of memory devices, an insulating encapsulation, and a redistribution circuit structure is provided. The memory devices are electrically connected to the integrated circuit. The integrated circuit and the memory devices are stacked, and the memory devices are embedded in the insulating encapsulation. The redistribution circuit structure is disposed on the insulating encapsulation, and the redistribution circuit structure is electrically connected to the integrated circuit and the memory devices. Furthermore, methods for fabricating the integrated fan-out package are also provided.
1. A chip package, comprising:
an integrated circuit chip comprising an active surface;
a plurality of memory chips stacked on the active surface of the integrated circuit chip and electrically connected to the integrated circuit chip;
an insulating encapsulation, laterally encapsulating the plurality of memory chips and partially covering the active surface of the integrated circuit chip; and
a redistribution circuit structure disposed on the plurality of memory chips and the insulating encapsulation, the redistribution circuit structure being electrically connected to the integrated circuit chip and the plurality of memory chips, wherein the active surface of the integrated circuit chip faces the plurality of memory chips.
2. The chip package as claimed in claim 1 further comprising a controller stacked over the plurality of memory chips, wherein the controller and the plurality of memory chips are laterally encapsulated by the insulating encapsulation.
3. The chip package as claimed in claim 2 , wherein the stacked memory chips and the controller are electrically connected to one another through bumps.
4. The chip package as claimed in claim 1 , wherein the integrated circuit chip further comprises a rear surface opposite to the active surface of the integrated circuit chip, and the integrated circuit chip is electrically connected to the plurality of memory chips through a plurality of bumps.
5. The chip package as claimed in claim 1 , wherein the plurality of memory chips are between the redistribution circuit structure and the integrated circuit chip.
6. The chip package as claimed in claim 1 further comprising a plurality of conductive pillars penetrating through the insulating encapsulation, wherein the integrated circuit chip is electrically connected to the redistribution circuit structure through the plurality of conductive pillars.
7. The chip package as claimed in claim 1 further comprising:
a plurality of conductive terminals electrically connected to the redistribution circuit structure, wherein the redistribution circuit structure is between the conductive terminals and the plurality of memory chips.
8. The chip package as claimed in claim 7 further comprising:
a package circuit substrate, wherein the redistribution circuit structure is electrically connected to the package circuit substrate through the plurality of conductive terminals.
9. A chip package, comprising:
an integrated circuit chip comprising an active surface and a rear surface opposite to the active surface, wherein the integrated circuit chip is encapsulated by a first insulating portion;
a plurality of memory chips stacked on the active surface of the integrated circuit chip and the first insulating portion, wherein the plurality of memory chips are electrically connected to the integrated circuit chip, the plurality of memory chips are encapsulated by a second insulating portion; and
a redistribution circuit structure disposed on the rear surface of the integrated circuit chip and the first insulating portion, the redistribution circuit structure being electrically connected to the integrated circuit chip and the plurality of memory chips, wherein the rear surface of the integrated circuit chip faces the redistribution circuit structure.
10. The chip package as claimed in claim 9 , wherein the second insulating portion partially covers the active surface of the integrated circuit chip and the first insulating portion.
11. The chip package as claimed in claim 9 further comprising:
a plurality of conductive pillars penetrating through the first insulating portion, the plurality of memory chips being electrically connected to the redistribution circuit structure through the conductive pillars; and
a redistribution layer on surfaces of the plurality of memory chips, wherein the integrated circuit chip is electrically connected to the plurality of memory chips through the redistribution circuit structure, the plurality of conductive pillars and the redistribution layer.
12. The chip package as claimed in claim 9 , wherein the integrated circuit chip is between the redistribution circuit structure and the plurality of memory chips.
13. The chip package as claimed in claim 9 further comprising:
a plurality of conductive terminals electrically connected to the redistribution circuit structure, wherein the redistribution circuit structure is between the conductive terminals and the integrated circuit chip.
14. The chip package as claimed in claim 13 further comprising:
a package circuit substrate, wherein the redistribution circuit structure is electrically connected to the package circuit substrate through the conductive terminals.
15. A chip package, comprising:
an integrated circuit chip comprising an active surface and a rear surface opposite to the active surface, wherein the integrated circuit chip is encapsulated by a first insulating portion;
a plurality of memory chips stacked on the rear surface of the integrated circuit chip and the first insulating portion, wherein the plurality of memory chips are electrically connected to the integrated circuit chip, the plurality of memory chips are encapsulated by a second insulating portion; and
a redistribution circuit structure disposed on the active surface of the integrated circuit chip and the first insulating portion, the redistribution circuit structure being electrically connected to the integrated circuit chip and the plurality of memory chips, wherein the active surface of the integrated circuit chip faces the redistribution circuit structure.
16. The chip package as claimed in claim 15 , wherein the second insulating portion partially covers the rear surface of the integrated circuit chip and the first insulating portion.
17. The chip package as claimed in claim 15 further comprising:
a plurality of conductive pillars penetrating through the first insulating portion, the plurality of memory chips being electrically connected to the redistribution circuit structure through the conductive pillars; and
a redistribution layer on surfaces of the plurality of memory chips, wherein the integrated circuit chip is electrically connected to the plurality of memory chips through the redistribution circuit structure, the plurality of conductive pillars and the redistribution layer.
18. The chip package as claimed in claim 15 , wherein the integrated circuit chip is between the redistribution circuit structure and the plurality of memory chips.
19. The chip package as claimed in claim 15 further comprising:
a plurality of conductive terminals electrically connected to the redistribution circuit structure, wherein the redistribution circuit structure is between the conductive terminals and the integrated circuit chip.
20. The chip package as claimed in claim 19 further comprising:
a package circuit substrate, wherein the redistribution circuit structure is electrically connected to the package circuit substrate through the conductive terminals.