Arrays of memory cells individually comprising a capacitor and a transistor and methods of forming such arrays
An array of memory cells individually comprising a capacitor and a transistor comprises, in a first level, alternating columns of digitlines and conductive shield lines. In a second level above the first level there are rows of transistor wordlines. In a third level above the second level there are rows and columns of capacitors. In a fourth level above the third level there are rows of transistor wordlines. In a fifth level above the fourth level there are alternating columns of digitlines and conductive shield lines. Other embodiments and aspects are disclosed, including method.
1. An array of memory cells individually comprising a capacitor and a transistor, comprising:
in a first level, alternating columns of digitlines and conductive shield lines;
in a second level above the first level, rows of transistor wordlines;
in a third level above the second level, rows and columns of capacitors;
in a fourth level above the third level, rows of transistor wordlines;
in a fifth level above the fourth level, alternating columns of digitlines and conductive shield lines; and
at least one of individual of the capacitors comprising a ferroelectric capacitor insulator or individual of the transistors comprising a ferroelectric gate insulator.
2. The array of claim 1 wherein the individual capacitors comprise a ferroelectric capacitor insulator.
3. The array of claim 1 wherein the individual transistors comprise a ferroelectric gate insulator.
4. The array of claim 1 wherein one of the first-level conductive shield lines is laterally between every immediately-adjacent of the first-level digitlines.
5. The array of claim 1 wherein the first-level columns of digitlines and the first-level columns of conductive shield lines alternate every-other-one with one another such that every immediately-adjacent of the first-level digitlines have one of the first-level conductive shield lines laterally there-between and such that every immediately-adjacent of the first-level conductive shield lines have one of the first-level digitlines laterally there-between.
6. The array of claim 1 wherein one of the fifth-level conductive shield lines is laterally between every immediately-adjacent of the fifth-level digitlines.
7. The array of claim 1 wherein the fifth-level columns of digitlines and the fifth-level columns of conductive shield lines alternate every-other-one with one another such that every immediately-adjacent of the fifth-level digitlines have one of the fifth-level conductive shield lines laterally there-between and such that every immediately-adjacent of the fifth-level conductive shield lines have one of the fifth-level digitlines laterally there-between.
8. The array of claim 1 wherein transistors in each of the second and fourth levels are elevationally-extending transistors.
9. The array of claim 1 wherein each of the capacitors has at least one capacitor electrode that is taller than it is wide.
10. The array of claim 1 wherein the memory cells individually have a total of only one transistor and a total of only one capacitor.
11. The array of claim 1 wherein the array is a first array and comprising another of said first array above said first array.
12. The array of claim 8 wherein each of the transistors in the second and fourth levels are vertical or within 10 0 of vertical.
13. The array of claim 9 wherein each of the capacitors has only one capacitor electrode that is taller than it is wide, each of the capacitors having its other capacitor electrode that is a common to all of the capacitors in the third level of the array, the common other electrode in the array being wider than it is tall.
14. The array of claim 9 wherein the one capacitor electrode is a pillar having a substantially circular periphery.
15. The array of claim 11 wherein the fifth level of the first array is the first level of the another of said first array such that the alternating columns of digitlines and conductive shield lines therein are shared by the first array and the another of said first array.
16. The array of claim 11 wherein the first level of the another of said first array is above the fifth level of the first array.
17. An array of memory cells individually comprising a capacitor and a transistor, comprising:
in a first level, alternating columns of digitlines and conductive shield lines;
in a second level above the first level, rows of transistor wordlines;
in a third level above the second level, rows and columns of capacitors;
in a fourth level above the third level, rows of transistor wordlines;
in a fifth level above the fourth level, alternating columns of digitlines and conductive shield lines; and
individual of the conductive shield lines being narrower than individual of the digitlines.
18. The array of claim 17 wherein one of the first-level conductive shield lines is laterally between every immediately-adjacent of the first-level digitlines.
19. The array of claim 17 wherein the first-level columns of digitlines and the first-level columns of conductive shield lines alternate every-other-one with one another such that every immediately-adjacent of the first-level digitlines have one of the first-level conductive shield lines laterally there-between and such that every immediately-adjacent of the first-level conductive shield lines have one of the first-level digitlines laterally there-between.
20. The array of claim 17 wherein one of the fifth-level conductive shield lines is laterally between every immediately-adjacent of the fifth-level digitlines.
21. The array of claim 17 wherein the fifth-level columns of digitlines and the fifth-level columns of conductive shield lines alternate every-other-one with one another such that every immediately-adjacent of the fifth-level digitlines have one of the fifth-level conductive shield lines laterally there-between and such that every immediately-adjacent of the fifth-level conductive shield lines have one of the fifth-level digitlines laterally there-between.
22. The array of claim 17 wherein each of the transistors in the second and fourth levels are vertical or within 10° of vertical.
23. The array of claim 17 wherein each of the capacitors has at least one capacitor electrode that is taller than it is wide.
24. The array of claim 17 wherein the array is a first array and comprising another of said first array above said first array.
25. The array of claim 23 wherein each of the capacitors has only one capacitor electrode that is taller than it is wide, each of the capacitors having its other capacitor electrode that is a common to all of the capacitors in the third level of the array, the common other electrode in the array being wider than it is tall.
26. The array of claim 23 wherein the one capacitor electrode is a pillar having a substantially circular periphery.
27. The array of claim 24 wherein the fifth level of the first array is the first level of the another of said first array such that the alternating columns of digitlines and conductive shield lines therein are shared by the first array and the another of said first array.
28. The array of claim 24 wherein the first level of the another of said first array is above the fifth level of the first array.