IP Library › Granted Patent US 10,784,348
Granted Patent B2
US 10,784,348 · App. 15/669,704 · Granted Sep 22, 2020

Porous semiconductor handle substrate

Inventors: Stephen Alan Fanelli (San Marcos, CA); Richard Hammond (Gwent, GB)
Assignee: QUALCOMM Incorporated
H01L29/1083H01L21/0203H01L21/02532H01L21/02595H01L21/2007H01L21/30604H01L21/6835H01L21/76256H01L21/78H01L21/84H01L23/3114H01L23/528H01L24/94H01L27/1203H01L29/7803H01L21/02203H01L24/11H01L24/13H01L2221/68304H01L2221/68359H01L2224/11H01L2224/13022H01L2924/00H01L2924/00014
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Quick Facts
Patent No.
US 10,784,348
App. No.
15/669,704
Granted
Sep 22, 2020
Kind
B2
Abstract

An integrated circuit (IC) may include an active device layer on a front-side surface of a semiconductor device substrate. The IC may also include a front-side dielectric layer having a first surface opposite a second surface, the first surface contacting the active device layer. The IC may further include a porous semiconductor handle substrate contacting the second surface of the front-side dielectric layer. The porous semiconductor handle substrate may be uniformly doped.

Claims (20)

1. An integrated circuit (IC), comprising:

an active device layer on a front-side surface of a semiconductor layer on an insulator layer of a semiconductor on insulator (SOI) device substrate;

a front-side dielectric layer having a first surface opposite a second surface, the first surface contacting the active device layer; and

a semiconductor handle substrate having a porous semiconductor layer contacting the second surface of the front-side dielectric layer and distal from the SOI device substrate, in which the semiconductor handle substrate is uniformly doped, and the porous semiconductor layer comprises a high porosity portion corresponding to dicing streets on the semiconductor device substrate, a first low porosity portion and a second low porosity portion adjacent to and side-by-side with the high porosity portion, the high porosity portion between the first low porosity portion and the second low porosity portion.

2. The IC of claim 1 , in which the porous semiconductor layer has a depth greater than 10 microns.

3. The IC of claim 1 , in which the semiconductor handle substrate comprises a bulk silicon wafer having the porous semiconductor layer.

4. The IC of claim 1 , in which the porous semiconductor layer is sealed or capped with oxide.

5. The IC of claim 1 , further comprising an oxide and/or adhesive between the porous semiconductor layer of the semiconductor handle substrate and the front-side dielectric layer.

6. The IC of claim 1 , further comprising an oxide within pores of the porous semiconductor layer of the semiconductor handle substrate.

7. The IC of claim 1 , in which the porous semiconductor layer comprises sealed oxide porous silicon.

8. The IC of claim 1 , in which the porous semiconductor layer comprises different porosities.

9. The IC of claim 1 , in which the porous semiconductor layer comprises different levels of porosity in different layers.

10. The IC of claim 9 , in which the different levels of porosity are graded or stepped.

11. The IC of claim 1 , in which the porous semiconductor layer comprises a 50 micron thick layer proximate to the front-side dielectric layer.

12. The IC of claim 1 , integrated into an RF front end module, the RF front end module incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.

13. An integrated circuit (IC), comprising:

an active device layer on a front-side surface of a semiconductor layer on an insulator layer of a semiconductor on insulator (SOI) device substrate;

a front-side dielectric layer having a first surface opposite a second surface, the first surface contacting the active device layer; and

means for reducing radio frequency (RF) harmonics contacting the second surface of the front-side dielectric layer and distal from the SOI device substrate, and the means for reducing RF harmonics comprising a high porosity portion corresponding to dicing streets on the semiconductor device substrate, a first low porosity portion and a second low porosity portion adjacent to and side-by-side with the high porosity portion, the high porosity portion between the first low porosity portion and the second low porosity portion.

14. The IC of claim 13 , integrated into an RF front end module, the RF front end module incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 4, 2017
From: FANELLI, STEPHEN ALAN; HAMMOND, RICHARD
To: QUALCOMM INCORPORATED
Reel/Frame 043783/0990 →
Continuity (2)
Provisional Application 62475730 · Mar 23, 2017
Related Publication 20180277632A1 · Sep 27, 2018
Cited By (3)
US 12,368,056 US 12,482,731 US 12,740,412