Selective capping processes and structures formed thereby
Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.
1. A method comprising:
forming a first conductive feature in a first dielectric layer, the first conductive feature having a metallic surface, the first dielectric layer having a dielectric surface;
modifying the dielectric surface to be hydrophobic by performing a surface modification treatment and forming a terminated surface, wherein the terminated surface is a self-aligned monolayer;
after modifying the dielectric surface, forming a capping layer on the metallic surface by performing a selective deposition process, wherein the selective deposition process does not deposit a material of the capping layer on the dielectric surface, wherein the capping layer comprises tungsten and has a concentration of chlorine that is less than 1%; and
forming a second dielectric layer over the capping layer and the dielectric surface.
2. The method of claim 1 , wherein the surface modification treatment comprises exposing the dielectric surface to a chemical, the chemical comprising a hydrophobic functional group, modifying the dielectric surface comprising terminating the dielectric surface with a species comprising the hydrophobic functional group.
3. The method of claim 2 , wherein the hydrophobic functional group has a general form of —C X H 2X+1 .
4. The method of claim 2 , wherein the chemical is a silane derivative.
5. The method of claim 2 , wherein the chemical is selected from the group consisting of tetramethylsilane (Si(CH 3 ) 4 ), N,N-Dimethyltrimethylsilylamine ((CH 3 ) 2 —N—Si—(CH 3 ) 3 ), or a combination thereof.
6. The method of claim 1 , wherein the surface modification treatment is a Chemical Vapor Deposition (CVD) process.
7. The method of claim 1 further comprising forming a second conductive feature through the second dielectric layer to the capping layer, wherein forming the first conductive feature comprises forming a gate structure over an active area on a substrate, a surface of the gate structure being the metallic surface.
8. The method of claim 7 , wherein the selective deposition process is an Atomic Layer Deposition (ALD) process, the ALD process comprising performing one or more cycles, each of the one or more cycles comprising:
flowing a tungsten chloride precursor; and
flowing a hydrogen precursor.
9. The method of claim 7 , wherein the surface of the gate structure is below a level of the dielectric surface of the first dielectric layer.
10. The method of claim 7 , wherein forming the gate structure further comprises recessing the gate structure, wherein the recessing forms the surface of the gate structure to be below a level of the dielectric surface of the first dielectric layer.
11. The method of claim 1 , wherein the capping layer has a thickness in a range from 30 Å to 50 Å.
12. A method of manufacturing a semiconductor device, the method comprising:
forming a first dielectric layer over a substrate;
forming a conductive feature, wherein after the forming the first dielectric layer and the forming the conductive feature the conductive feature is located within the first dielectric layer;
after the forming the conductive feature, terminating the first dielectric layer with a species comprising a hydrophobic functional group to form a dielectric surface, the terminating the first dielectric layer forming a terminated surface, wherein the terminated surface is a self-aligned monolayer;
forming a metal cap on the conductive feature without forming a material of the metal cap over on the dielectric surface, wherein the metal cap comprises tungsten and has a concentration of chlorine that is less than 1%; and
forming a second dielectric layer on the dielectric surface and the metal cap.
13. The method of claim 12 , wherein a surface of the conductive feature, on which the metal cap is disposed, is level with the dielectric surface.
14. The method of claim 12 , wherein the hydrophobic functional group is a hydrocarbon.
15. The method of claim 12 , wherein the hydrophobic functional group has a general form of —C X H 2X+ .
16. The method of claim 12 , wherein the metal cap has a thickness in a range from 30 Å to about 50 Å.
17. A method of manufacturing a semiconductor device, the method comprising:
forming a gate structure over an active area on a substrate;
forming a first dielectric layer over the substrate and along the gate structure;
terminating surfaces of the first dielectric layer with a chemical selected from the group consisting of tetramethylsilane (Si(CH 3 ) 4 ), N,N-Dimethyltrimethylsilylamine ((CH 3 ) 2 —N—Si—(CH 3 ) 3 ), or a combination thereof, wherein the terminated surface is a self-aligned monolayer;
forming a metal cap on the gate structure, wherein the metal cap comprises tungsten and has a concentration of chlorine that is less than 1%;
forming a second dielectric layer over the metal cap and the first dielectric layer; and
forming a conductive feature through the second dielectric layer to the metal cap.
18. The method of claim 17 , wherein the metal cap has a thickness in a range from 30 Å to 50 Å.
19. The method of claim 17 , wherein a bottom surface of the metal cap is level with a top surface of the first dielectric layer.
20. The method of claim 17 , wherein the forming the gate structure comprises:
forming a gate dielectric layer having a first horizontal portion, a first vertical portion, and a second vertical portion;
forming a work-function tuning layer having a second horizontal portion, a third vertical portion, and a fourth vertical portion, the second horizontal portion of the work-function tuning layer being over the first horizontal portion of the gate dielectric layer, the third vertical portion and the fourth vertical portion of the work-function tuning layer being disposed laterally between the first vertical portion and the second vertical portion of the gate dielectric layer; and
forming a gate electrode disposed laterally between the third vertical portion and the fourth vertical portion of the work-function tuning layer, wherein the metal cap is on top surfaces of the gate electrode and the third vertical portion and the fourth vertical portion of the work-function tuning layer.