Manufacturing method for high-electron-mobility transistor
Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a semiconductive substrate. A donor-supply layer is over the semiconductive substrate. The donor-supply layer includes a top surface. A gate structure, a drain, and a source are over the donor-supply layer. A passivation layer covers conformally over the gate structure and the donor-supply layer. A gate electrode is over the gate structure. A field plate is disposed on the passivation layer between the gate electrode and the drain. The field plate includes a bottom edge. The gate electrode having a first edge in proximity to the field plate, the field plate comprising a second edge facing the first edge, a horizontal distance between the first edge and the second edge is in a range of from about 0.05 to about 0.5 micrometers.
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a semiconductor layer over the substrate, wherein the semiconductor layer comprises a donor-supply layer;
forming a gate structure over the semiconductor layer, wherein the donor-supply layer is under and across the gate structure;
forming a passivation layer over the gate structure and the semiconductor layer;
forming a first opening non-overlapping with the gate structure in the passivation layer to expose the donor-supply layer;
forming a drain by blanket depositing a conductive layer over the gate structure, the passivation layer, and the opening;
forming a field plate on the passivation layer by patterning the conductive layer; and
forming a second opening exposing the gate structure after forming the field plate.
2. The method of claim 1 , wherein the field plate is formed more in proximity to the gate structure than the drain.
3. The method of claim 2 , further comprising depositing a capping layer over the field plate.
4. The method of claim 2 , further comprising concurrently patterning the conductive layer to form a drain contact over the drain, the drain contact being wider than the drain.
5. The method of claim 3 , wherein the patterning the conductive layer comprises further removing a portion of the passivation layer exposed from the conductive layer after patterning the conductive layer and forming a recess in the passivation layer.
6. The method of claim 5 , wherein the capping layer fills the recess.
7. The method of claim 4 , wherein a thickness of the drain contact is substantially identical to a thickness of field plate.
8. A method of manufacturing a semiconductor device, comprising:
receiving a substrate;
forming a semiconductor layer over the substrate;
forming a gate structure over the semiconductor layer;
forming a passivation layer over the gate structure and the semiconductor layer;
forming a first opening non-overlapping with the gate structure in the passivation layer;
depositing a conductive layer in the first opening and covers a portion of the passivation layer;
forming a field plate on the passivation layer by patterning the conductive layer; and
forming a second opening exposing the gate structure after forming the field plate.
9. The method of claim 8 , wherein the depositing the conductive layer comprises blanket depositing the conductive layer over the gate structure and the semiconductor layer.
10. The method of claim 9 , further comprising patterning the conductive layer to form a drain contact.
11. The method of claim 10 , wherein the patterning the conductive layer comprises removing a portion of the passivation layer underlying the conductive layer and forming a recess having a bottom surface.
12. The method of claim 11 , wherein the bottom surface of the recess is lower than a bottom surface of the drain contact.
13. The method of claim 8 , further comprising forming a capping layer over the field plate.
14. The method of claim 13 , wherein the forming the capping layer is prior to forming the second opening.
15. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a semiconductor layer over the substrate;
forming a gate structure over the semiconductor layer;
forming a passivation layer over the gate structure and the semiconductor layer;
forming a first opening non-overlapping with the gate structure in the passivation layer;
depositing a conductive layer in the first opening and covers a portion of the passivation layer;
forming a field plate disposed on the passivation layer by patterning the conductive layer;
forming a second opening exposing the gate structure after forming the field plate; and
forming a gate electrode comprising a vertical portion upward-extending from the gate structure, and a horizontal portion laterally extending over the field plate.
16. The method of claim 15 , wherein the horizontal portion of the gate electrode is wider than the gate structure.
17. The method of claim 15 , wherein the passivation layer surrounds the vertical portion of the gate electrode.
18. The method of claim 15 , wherein a bottom edge of the field plate is in contact with the passivation layer.
19. The method of claim 15 , further comprising forming a capping layer over the field plate and the passivation layer.
20. The method of claim 15 , further comprising forming a protection layer between the gate structure and the passivation layer.