Flip-chip high speed components with underfill
A flip-chip manufacture is described. Methods of blocking adhesive underfill in flip-chip high speed component manufacture include creating topology discontinuities to prevent adhesive underfill material from interacting with RF sensitive regions on substrates.
1. A flip-chip structure utilizing two adjacent layers which are a first layer and a second layer, the flip-chip structure comprising:
one or more electrical connectors providing connectivity between the two adjacent layers;
a topology discontinuity formed, on a surface of the first layer, outside at least one sensitive region of the flip-chip structure, wherein a height of the topology discontinuity in a direction extending from the surface of the first layer toward the second layer is less than a height of the one or more electrical connectors, and wherein the topology discontinuity is one of a surface variation and a surface roughness of the first layer; and
adhesive underfill material, between a pair of opposed surfaces of the two adjacent layers, substantially outside the at least one sensitive region due to the topology discontinuity to create a substantially adhesive underfill material-free region.
2. The flip-chip structure as claimed in claim 1 , the topology discontinuity being configured to snag a liquid meniscus of the adhesive underfill material.
3. The flip-chip structure as claimed in claim 1 , the topology discontinuity being configured to snag a liquid meniscus of a non-adhesive underfill material immiscible with the adhesive underfill material.
4. The flip-chip structure as claimed in claim 1 , wherein the substantially adhesive underfill material-free region is vented.
5. The flip-chip structure as claimed in claim 1 , wherein a portion of the topology discontinuity extends to an edge of the flip-chip structure and a via in one of the first layer and the second layer is configured to vent the substantially adhesive underfill material-free region.
6. The flip-chip structure as claimed in claim 1 , wherein the sensitive region comprises an area around the one or more electrical connectors.
7. The flip-chip structure as claimed in claim 6 , wherein the one or more electrical connectors comprise at least one of solder balls, gold ball bumps, gold stud bumps, copper pillars and pads.
8. The flip-chip structure as claimed in claim 1 , wherein the two adjacent layers having different coefficients of thermal expansion.
9. The flip-chip structure as claimed in claim 1 , wherein the first layer is a silicon photonics chip and the second layer is a substrate of a different technology than the silicon photonics chip.
10. The flip-chip structure as claimed in claim 9 , wherein the silicon photonics chip includes high-speed Radio Frequency (RF) circuits which interact with the adhesive underfill material, and wherein the high-speed RF circuits are in the at least one sensitive region.
11. The flip-chip structure as claimed in claim 1 , wherein the topology discontinuity is surface roughness provided via one of incomplete sputtering, superficial surface etching, removing an oxide layer of a passivation layer, and scribing.
12. The flip-chip structure as claimed in claim 1 , wherein the topology discontinuity is surface roughness that is one or more of discontinuous, dotted, and dashed on the bottom of the first layer.
13. The flip-chip structure as claimed in claim 12 , wherein a dimension for the surface roughness is dependent on a surface tension of the adhesive underfill material.
14. A method for providing a flip-chip structure utilizing two adjacent layers which are a first layer and a second layer, the flip-chip structure comprising:
providing one or more electrical connectors providing connectivity between the two adjacent layers;
providing a topology discontinuity formed, on a surface of the first layer, outside at least one sensitive region of the flip-chip structure, wherein a height of the topology discontinuity in a direction extending from the surface of the first layer toward the second layer is less than a height of the one ore more electrical connectors, and wherein the topology discontinuity is one of a surface variation and a surface roughness surface of the first layer; and
providing adhesive underfill material, between a pair of opposed surfaces of the two adjacent layers, substantially outside the at least one sensitive region due to the topology discontinuity to create a substantially adhesive underfill material-free region.
15. The method as claimed in claim 14 , the topology discontinuity being configured to snag a liquid meniscus of the adhesive underfill material.
16. The method as claimed in claim 14 , the topology discontinuity being configured to snag a liquid meniscus of a non-adhesive underfill material immiscible with the adhesive underfill material.
17. The method as claimed in claim 14 , wherein the substantially adhesive underfill material-free region is vented.
18. The method as claimed in claim 14 , wherein a portion of the topology discontinuity extends to an edge of the flip-chip structure and a via in one of the first layer and the second layer is configured to vent the substantially adhesive underfill material-free region.
19. The method as claimed in claim 14 , wherein the sensitive region comprises an area around the one or more electrical connectors.