Photonic package laser area macro-void pressure relief micro-channels
Embodiments disclosed herein include electronic packages with vents to prevent pressure buildup below a die. In an embodiment, an electronic package comprises a package substrate and a die attached to the package substrate by interconnects. In an embodiment, an underfill is under the die and surrounds the interconnects. In an embodiment, a void is provided in the underfill, and a vent is in the underfill. In an embodiment, the vent is fluidically coupled to the void and extends to an edge of the underfill.
1. An electronic package, comprising:
a package substrate;
a die attached to the package substrate by interconnects, the interconnect comprising bumps having a pitch;
an underfill under the die and surrounding the interconnects, wherein a void is in the underfill;
a first vent along a first direction, wherein the first vent is fluidically coupled to the void and extends to an edge of the underfill, wherein the first vent is between a first bump and a second bump of the bumps having the pitch, and wherein a third bump of the bumps is spaced apart from the second bump by the pitch; and
a second vent, wherein the second vent intersects the void and extends to the edge of the underfill, the second vent along a second direction orthogonal to the first direction.
2. The electronic package of claim 1 , wherein the die is a photonics integrated circuit (PIC).
3. The electronic package of claim 2 , wherein a laser on the die is positioned over the void.
4. The electronic package of claim 1 , wherein the first vent exposes a surface of the package substrate.
5. The electronic package of claim 1 , wherein the underfill is between the first vent and the die.
6. The electronic package of claim 1 , wherein the first vent has a height that is less than a standoff distance between the package substrate and the die.
7. The electronic package of claim 6 , wherein the height of the first vent is approximately 20 μm or less.
8. The electronic package of claim 1 , wherein a width of the first vent is approximately 20 μm or less.
9. The electronic package of claim 1 , wherein the void is surrounded by a trench in the package substrate.
10. The electronic package of claim 1 , further comprising:
a second void in the underfill; and
a third vent, wherein the third vent intersects the second void and extends to the edge of the underfill.
11. An electronic package, comprising:
a package substrate;
a die attached to the package substrate by a plurality of interconnects, the interconnect comprising bumps having a pitch;
an underfill surrounding the plurality of interconnects;
a first vent in the underfill, the first vent along a first direction, wherein the first vent extends to an edge of the underfill, wherein the first vent is between a first bump and a second bump of the bumps having the pitch, and wherein a third bump of the bumps is spaced apart from the second bump by the pitch; and
a second vent, wherein the second vent extends to the edge of the underfill, the second vent along a second direction orthogonal to the first direction.
12. The electronic package of claim 11 , wherein the plurality of interconnects are flip-chip interconnects.
13. The electronic package of claim 12 , wherein the first vent has a height that is less than a standoff distance between the package substrate and the die.
14. The electronic package of claim 13 , wherein the height is approximately 20 μm or less.
15. The electronic package of claim 11 , wherein a width of the first vent is approximately 20 μm or less.
16. The electronic package of claim 11 , further comprising:
a void in the underfill within a perimeter of the die, wherein the void is intersected by the first vent.
17. The electronic package of claim 11 , wherein the die comprises a microelectromechanical system (MEMS) device.
18. The electronic package of claim 11 , wherein the underfill is between the first vent and the die.
19. An electronic system, comprising:
a board;
a package substrate attached to the board;
a die attached to the package substrate by interconnects, the interconnect comprising bumps having a pitch;
an underfill under the die and surrounding the interconnects, wherein a void is in the underfill;
a first vent along a first direction, wherein the first vent is fluidically coupled to the void and extends to an edge of the underfill, wherein the first vent is between a first bump and a second bump of the bumps having the pitch, and wherein a third bump of the bumps is spaced apart from the second bump by the pitch; and
a second vent, wherein the second vent intersects the void and extends to the edge of the underfill, the second vent along a second direction orthogonal to the first direction.
20. The electronic system of claim 19 , wherein the first vent has a thickness that is less than a standoff height between the package substrate and the die.