IP Library › Granted Patent US 10,811,440
Granted Patent B2
US 10,811,440 · App. 16/291,080 · Granted Oct 20, 2020

Semiconductor device, display device, and electronic appliance

Inventor: Hajime Kimura (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/124G09G3/3233G09G3/3241H01L27/1225H01L27/1255H01L27/3206H01L27/3276G09G3/3266G09G3/3648G09G2300/0842G09G2310/0248G09G2310/0262G09G2310/08H01L27/3244
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Quick Facts
Patent No.
US 10,811,440
App. No.
16/291,080
Granted
Oct 20, 2020
Kind
B2
Abstract

In case the size of the transistor is enlarged, power consumption of the transistor is increased. Thus, the present invention provides a display device capable of preventing a current from flowing to a display element in signal writing operation without varying potentials of power source lines for supplying a current to the display element per row. In setting a gate-source voltage of a transistor by applying a predetermined current to the transistor, a potential of a gate terminal of the transistor is adjusted so as to prevent a current from flowing to a load connected to a source terminal of the transistor. Therefore, a potential of a wire connected to the gate terminal of the transistor is differentiated from a potential of a wire connected to a drain terminal of the transistor.

Claims (95)

1. A display device comprising:

a light emitting element;

a first transistor;

a second transistor;

a third transistor;

a capacitor;

a first wiring;

a second wiring;

a third wiring;

a fourth wiring; and

a fifth wiring,

wherein an electrode of the light emitting element is electrically connected to one of a source and a drain of the first transistor,

wherein the capacitor is electrically connected between the one of the source and the drain of the first transistor and a gate of the first transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to the first wiring,

wherein the electrode of the light emitting element is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring,

wherein a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to the third wiring,

wherein a gate of the second transistor is electrically connected the fourth wiring,

wherein a gate of the third transistor is electrically connected to the fifth wiring,

wherein the capacitor comprises a first electrode, a first insulating film, a second electrode, a second insulating film, and a third electrode,

wherein the first insulating film is over the first electrode,

wherein the semiconductor layer of the first transistor and the second electrode are over the first insulating film,

wherein the second insulating film is over the semiconductor layer of the first transistor and the second electrode,

wherein the second insulating film comprises an opening portion,

wherein the light emitting element overlaps the opening portion,

wherein the third electrode is over the second insulating film, and

wherein each of the semiconductor layer of the first transistor and the second electrode comprises In, Ga and Zn.

2. The display device according to claim 1 ,

wherein the first transistor is a driving transistor.

3. The display device according to claim 1 ,

wherein a source electrode and a drain electrode of the first transistor are over the second insulating film.

4. A display device comprising:

a light emitting element;

a transistor;

a first switch;

a second switch;

a capacitor;

a first wiring;

a second wiring;

a third wiring;

a fourth wiring; and

a fifth wiring,

wherein an electrode of the light emitting element is electrically connected to one of a source and a drain of the transistor,

wherein the capacitor is electrically connected between the one of the source and the drain of the transistor and a gate of the transistor,

wherein the other of the source and the drain of the transistor is electrically connected to the first wiring,

wherein the electrode of the light emitting element is electrically connected to the second wiring via the first switch,

wherein a gate of the transistor is electrically connected to the third wiring via the second switch,

wherein the first switch is configured such that an on state and an off state of the first switch are controlled by a signal input to the fourth wiring,

wherein the second switch is configured such that an on state and an off state of the second switch are controlled by a signal input to the fifth wiring,

wherein the capacitor comprises a first electrode, a first insulating film, a second electrode, a second insulating film, and a third electrode,

wherein the first insulating film is over the first electrode,

wherein the semiconductor layer of the transistor and the second electrode are over the first insulating film,

wherein the second insulating film is over the semiconductor layer of the transistor and the second electrode,

wherein the second insulating film comprises an opening portion,

wherein the light emitting element overlaps the opening portion,

wherein the third electrode is over the second insulating film, and

wherein each of the semiconductor layer of the transistor and the second electrode comprises In, Ga and Zn.

5. The display device according to claim 4 ,

wherein the transistor is a driving transistor.

6. The display device according to claim 4 ,

wherein a source electrode and a drain electrode of the transistor are over the second insulating film.

7. A display device comprising:

a light emitting element;

a first transistor;

a second transistor;

a third transistor;

a capacitor;

a first wiring;

a second wiring;

a third wiring;

a fourth wiring; and

a fifth wiring,

wherein an electrode of the light emitting element is electrically connected to one of a source and a drain of the first transistor,

wherein the capacitor is electrically connected between the one of the source and the drain of the first transistor and a gate of the first transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to the first wiring,

wherein the electrode of the light emitting element is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring,

wherein a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to the third wiring,

wherein a gate of the second transistor is electrically connected the fourth wiring,

wherein a gate of the third transistor is electrically connected to the fifth wiring,

wherein the capacitor comprises a first electrode, a first insulating film, a second electrode, a second insulating film, and a third electrode,

wherein the first insulating film is over the first electrode,

wherein the semiconductor layer of the first transistor and the second electrode are over and in contact with the first insulating film,

wherein the second insulating film is over and in contact with the semiconductor layer of the first transistor and the second electrode,

wherein the second insulating film comprises an opening portion,

wherein the light emitting element overlaps the opening portion, and

wherein the third electrode is over and in contact with the second insulating film.

8. The display device according to claim 7 ,

wherein each of the semiconductor layer of the transistor and the second electrode comprises polysilicon.

9. The display device according to claim 7 ,

wherein the first transistor is a driving transistor.

10. The display device according to claim 7 ,

wherein a source electrode and a drain electrode of the first transistor are over the second insulating film.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 4, 2019
From: KIMURA, HAJIME
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 048494/0307 →
Priority Claims (1)
JP 2005-191145 · Jun 30, 2005 · national
Continuity (5)
Continuation 15496092 · Apr 25, 2017
Continuation 14644384 · Mar 11, 2015
Continuation 12716840 · Mar 3, 2010
Continuation 11425242 · Jun 20, 2006
Related Publication 20190237481A1 · Aug 1, 2019