Semiconductor package including heat sink

1. A semiconductor package, comprising:

a package base substrate;

at least one semiconductor chip on the package base substrate such that an active surface of the at least one semiconductor chip faces the package base substrate;

a heat sink attached on an inactive surface opposite to the active surface of the at least one semiconductor chip, the heat sink including a base and a plurality of protrusion patterns on a top of the base; and

a molding covering a top of the package base substrate, a side surface of the at least one semiconductor chip, and a side surface of the heat sink without covering a top of the heat sink,

wherein:

the molding includes a filler, and

a diameter of particles of the filler is greater than an interval between adjacent protrusion patterns of the plurality of protrusion patterns.

2. The semiconductor package as claimed in claim 1 , wherein:

the at least one semiconductor chip includes a plurality of semiconductor chip pads on an active surface,

the package base substrate includes a plurality of first connection pads on a top of the package base substrate, and

the plurality of semiconductor chip pads is electrically connected to each of the plurality of first connection pads through a plurality of chip connection terminal attached on the plurality of semiconductor chip pads.

3. The semiconductor package as claimed in claim 1 , wherein an uppermost end of the molding and a top of each of the plurality of protrusion patterns of the heat sink are on a same level.

4. The semiconductor package as claimed in claim 1 , wherein the plurality of protrusion patterns of the heat sink is arranged in a honeycomb structure on the top of the base.

5. The semiconductor package as claimed in claim 1 , wherein each protrusion pattern of the plurality of protrusion patterns has a circular horizontal cross-sectional surface.

6. The semiconductor package as claimed in claim 1 , further comprising:

a bonding wire electrically connecting the at least one semiconductor chip to the package base substrate; and

a heat sink attach film between the at least one semiconductor chip and the heat sink, the heat sink attach film having a same horizontal area as a horizontal area of the heat sink,

wherein:

a portion of the bonding wire is buried in the heat sink attach film, and

the bonding wire is spaced apart from the heat sink without contacting the heat sink.

7. The semiconductor package as claimed in claim 1 , wherein:

a horizontal area of the heat sink is greater than a horizontal area of the at least one semiconductor chip, and

the heat sink overlaps all of the at least one semiconductor chip in a vertical direction.

8. The semiconductor package as claimed in claim 1 , wherein a horizontal area of the heat sink is the same as a horizontal area of the at least one semiconductor chip.

9. The semiconductor package as claimed in claim 1 , further comprising an electromagnetic shield covering a side surface of the package base substrate, a side surface and a top of the molding, and a top of the heat sink.

10. The semiconductor package as claimed in claim 9 , wherein a portion of the electromagnetic shield on the heat sink forms an embossing pattern that includes a top having a concave-convex structure.

11. The semiconductor package as claimed in claim 9 , wherein the electromagnetic shield fills a space between protrusion patterns of the plurality of protrusion patterns and has a flat top on the heat sink.

12. A semiconductor package, comprising:

a package base substrate, the package base substrate including a plurality of first connection pads on a top of the package base substrate and a plurality of second connection pads on a bottom of the package base substrate;

a semiconductor chip on the package base substrate such that an active surface of the semiconductor chip faces the package base substrate, the semiconductor chip including a plurality of semiconductor chip pads on the active surface, the plurality of semiconductor chip pads being electrically connected to each of the plurality of first connection pads;

a heat sink attached on the semiconductor chip, the heat sink including a base and a plurality of protrusion patterns on a top of the base;

a molding covering a top of the package base substrate, a side surface of the semiconductor chip, and a side surface of the heat sink without covering a top of the heat sink; and

a plurality of external connection terminals attached on the plurality of second connection pads,

wherein:

the molding includes a filler, and

a diameter of particles of the filler is greater than an interval between adjacent protrusion patterns of the plurality of protrusion patterns.

13. The semiconductor package as claimed in claim 12 , wherein an uppermost end of the molding and a top of each of the plurality of protrusion patterns of the heat sink are on a same level.

14. The semiconductor package as claimed in claim 12 , wherein the plurality of protrusion patterns of the heat sink is arranged in a honeycomb structure on the top of the base.

15. The semiconductor package as claimed in claim 12 , wherein each protrusion pattern of the plurality of protrusion patterns has a circular horizontal cross-sectional surface.

16. The semiconductor package as claimed in claim 12 , wherein a horizontal area of the heat sink is the same as a horizontal area of the semiconductor chip.

17. The semiconductor package as claimed in claim 12 , further comprising an electromagnetic shield covering a side surface of the package base substrate, a side surface and a top of the molding, and a top of the heat sink,

wherein a portion of the electromagnetic shield on the heat sink forms an embossing pattern that includes a top having a concave-convex structure.

18. The semiconductor package as claimed in claim 12 , further comprising an electromagnetic shield covering a side surface of the package base substrate, a side surface and a top of the molding, and a top of the heat sink,

wherein the electromagnetic shield fills a space between protrusion patterns of the plurality of protrusion patterns and has a flat top on the heat sink.

19. The semiconductor package as claimed in claim 12 , wherein the semiconductor chip includes a plurality of chips that are vertically stacked on the package base substrate.