Tapered fin-type field-effect transistors

1. A structure for a fin-type field-effect transistor, the structure comprising:

a semiconductor fin having a top surface;

a first pillar in the semiconductor fin, the first pillar extending through a height of the semiconductor fin and across a width of the semiconductor fin;

a second pillar in the semiconductor fin, the second pillar extending through the height of the semiconductor fin and across the width of the semiconductor fin;

a third pillar in the semiconductor fin, the third pillar extending through the height of the semiconductor fin and across the width of the semiconductor fin, and the third pillar arranged along a length of the semiconductor fin between the first pillar and the second pillar;

a first gate structure extending over the first pillar;

a second gate structure extending over the second pillars;

a first sidewall spacer on the top surface of the semiconductor fin, the first sidewall spacer positioned adjacent to the third pillar and the first gate structure; and

a third gate structure extending over a first portion of the semiconductor fin,

wherein the first pillar and the second pillar are comprised of a first dielectric material, the third pillar is comprised of a second dielectric material, the second gate structure is arranged along the length of the semiconductor fin between the first gate structure and the third gate structure, the third pillar is arranged along the length of the semiconductor fin between the first pillar and the second pillar, a second portion of the semiconductor fin is arranged along the length of the semiconductor fin between the first pillar and the third pillar, a third portion of the semiconductor fin is arranged along the length of the semiconductor fin between the second pillar and the third pillar, and the second portion of the semiconductor fin is arranged vertically beneath the first sidewall spacer.

2. The structure of claim 1 wherein the first pillar has a first height, and the third pillar has a second height that is greater than the first height.

3. The structure of claim 1 further comprising:

a second sidewall spacer on the top surface of the semiconductor fin, the second sidewall spacer positioned adjacent to the second gate structure and between the second gate structure and the third gate structure, and the third portion of the semiconductor fin arranged vertically beneath the second sidewall spacer.

4. The structure of claim 1 wherein the first dielectric material is different in composition from the second dielectric material.

5. The structure of claim 4 wherein the first dielectric material is silicon dioxide, and the second dielectric material is silicon nitride.

6. The structure of claim 4 wherein the first pillar and the second pillar have a first height, and the third pillar has a second height that is greater than the first height.

7. The structure of claim 1 wherein the semiconductor fin is free of a source/drain region beneath the second pillar.

8. The structure of claim 3 wherein the second portion of the semiconductor fin is arranged directly between the first pillar and the third pillar, and the third portion of the semiconductor fin is arranged directly between the second pillar and the third pillar.

9. The structure of claim 1 wherein the semiconductor fin is arranged over a substrate, the first pillar, the second pillar, and the third pillar each extend fully through a thickness of the semiconductor fin, and the first pillar, the second pillar, and the third pillar each include a portion positioned in the substrate beneath the semiconductor fin.

10. The structure of claim 1 wherein the third pillar extends above the top surface of the semiconductor fin.