Semiconductor device and method

1. A method comprising:

forming, in an insulating layer, a first set of source/drain contact openings, wherein the insulating layer covers: (i) a first elongated semiconductor structure extending in a first horizontal direction along a substrate and protruding vertically above the substrate, and (ii) a second elongated semiconductor structure extending along the substrate in parallel with the first semiconductor structure and protruding vertically above the substrate, wherein the first set of source/drain contact openings are formed above a first set of regions of an upper portion of the first semiconductor structure,

wherein forming the first set of source/drain contact openings comprises forming a first source/drain contact opening above a first region of the first set of regions of the first semiconductor structure, wherein the first source/drain contact opening includes: (i) a first deep portion formed directly above the first region of the first semiconductor structure, and (ii) a first shallow portion formed adjacent to the first deep portion and extending vertically through the insulating layer, such that a level of a bottom surface of the first shallow portion is located above a level of a directly opposite first region of an upper portion of the second semiconductor structure, wherein the first shallow portion protrudes from the first deep portion in a second horizontal direction towards the first region of the second semiconductor structure and to a horizontal position disposed at least halfway between the first semiconductor structure and the second semiconductor structure;

wherein forming the first source/drain contact opening comprises:

forming the first deep portion by etching the insulating layer above the first region of the first semiconductor structure,

filling, at least partially, the first deep portion with a fill material,

forming the first shallow portion by etching the insulating layer selectively to the fill material adjacent to the first deep portion, and

removing the fill material in the first deep portion by etching the fill material selectively to the insulating layer;

forming a first set of source/drain contacts in the first set of source/drain contact openings, wherein forming the first set of source/drain contacts comprises forming a first source/drain contact in the first source/drain contact opening, wherein the first source/drain contact includes: (i) a first vertically extending contact portion arranged in the first deep portion and (ii) a first via landing portion arranged in the first shallow portion and protruding horizontally from the first vertically extending contact portion; and

forming an interconnection level, the interconnection level including a first vertical via abutting the first via landing portion.

2. The method according to claim 1 , wherein a set of gate structures extends across the first semiconductor structure and the second semiconductor structure, wherein the set of gate structures are embedded by the insulating layer, and wherein each of the regions of the first semiconductor structure and the second semiconductor structure is a region formed adjacent to at least one gate structure of the set of gate structures.

3. The method according to claim 1 , further comprising:

subsequent to forming the first set of source/drain contact openings and prior to forming the first set of source/drain contacts, epitaxially growing a respective doped semiconductor top portion in each region of the first set of regions.

4. The method according to claim 1 , wherein forming the first set of source/drain contacts comprises depositing a contact material in the first set of source/drain openings, and wherein the method further comprises forming a capping layer on the first set of source/drain contacts.

5. The method according to claim 1 , wherein the first semiconductor structure and, the second semiconductor structure form part of a functional cell, wherein forming the interconnection level comprises forming the interconnection level to include a middle routing track extending in the first horizontal direction and arranged at a horizontal position halfway between the first and second semiconductor structures, and wherein the middle routing track abuts the first vertical via.

6. A method comprising:

forming, in an insulating layer, a first set of source/drain contact openings, wherein the insulating layer covers: (i) a first elongated semiconductor structure extending in a first horizontal direction along a substrate and protruding vertically above the substrate, and (ii) a second elongated semiconductor structure extending along the substrate in parallel with the first semiconductor structure and protruding vertically above the substrate, wherein the first set of source/drain contact openings are formed above a first set of regions of an upper portion of the first semiconductor structure,

wherein forming the first set of source/drain contact openings comprises forming a first source/drain contact opening above a first region of the first set of regions of the first semiconductor structure, wherein the first source/drain contact opening includes: (i) a first deep portion formed directly above the first region of the first semiconductor structure, and (ii) a first shallow portion formed adjacent to the first deep portion and extending vertically through the insulating layer, such that a level of a bottom surface of the first shallow portion is located above a level of a directly opposite first region of an upper portion of the second semiconductor structure, wherein the first shallow portion protrudes from the first deep portion in a second horizontal direction towards the first region of the second semiconductor structure and to a horizontal position disposed at least halfway between the first semiconductor structure and the second semiconductor structure;

wherein forming the first source/drain contact opening comprises:

forming, on the insulating layer, a first contact etch mask that includes a first opening above the first region of the first semiconductor structure,

forming the first deep portion by etching the insulating layer through the first opening,

depositing a fill material layer covering the first contact etch mask and filling the first deep portion,

forming, on the fill material layer, a second contact etch mask that includes a second opening above a region of the insulating layer adjacent to the first deep portion,

etching the fill material layer through the second opening, such that (i) a portion of the first contact etch mask formed above the region of the insulating layer adjacent to the first deep portion is exposed and (ii) a portion of the fill material layer remains in the first deep portion,

removing the portion of the first contact etch mask to expose the region of the insulating layer adjacent to the first deep portion, thereby fixating an enlarged opening in the first contact etch mask,

forming the first shallow portion by etching the insulating layer through the enlarged opening selectively to the fill material layer portion, and

removing the fill material in the first deep portion by etching the fill material selectively to the insulating layer;

forming a first set of source/drain contacts in the first set of source/drain contact openings, wherein forming the first set of source/drain contacts comprises forming a first source/drain contact in the first source/drain contact opening, wherein the first source/drain contact includes: (i) a first vertically extending contact portion arranged in the first deep portion and (ii) a first via landing portion arranged in the first shallow portion and protruding horizontally from the first vertically extending contact portion; and

forming an interconnection level, the interconnection level including a first vertical via abutting the first via landing portion.

7. The method according to claim 6 , wherein a set of gate structures, extends across the first semiconductor structure and the second semiconductor structure, wherein the set of gate structures are embedded by the insulating layer, and wherein each of the regions of the first semiconductor structure and the second semiconductor structure is a region formed adjacent to at least one gate structure of the set of gate structures.

8. The method according to claim 6 , further comprising:

subsequent to forming the first set of source/drain contact openings and prior to forming the first set of source/drain contacts, epitaxially growing a respective doped semiconductor top portion in each region of the first set of regions.

9. The method according to claim 6 , wherein forming the first set of source/drain contacts comprises depositing a contact material in the first set of source/drain openings, and wherein the method further comprises forming a capping layer on the first set of source/drain contacts.

10. The method according to claim 6 , wherein the first semiconductor structure and the second semiconductor structure form part of a functional cell, wherein forming the interconnection level comprises forming the interconnection level to include a middle routing track extending in the first horizontal direction and arranged at a horizontal position halfway between the first and second semiconductor structures, and wherein the middle routing track abuts the first vertical via.

11. A method comprising:

forming, in an insulating layer, a first set of source/drain contact openings, wherein the insulating layer covers: (i) a first elongated semiconductor structure extending in a first horizontal direction along a substrate and protruding vertically above the substrate, and (ii) a second elongated semiconductor structure extending along the substrate in parallel with the first semiconductor structure and protruding vertically above the substrate, wherein the first set of source/drain contact openings are formed above a first set of regions of an upper portion of the first semiconductor structure,

wherein forming the first set of source/drain contact openings comprises forming a first source/drain contact opening above a first region of the first set of regions of the first semiconductor structure, wherein the first source/drain contact opening includes: (i) a first deep portion formed directly above the first region of the first semiconductor structure, and (ii) a first shallow portion formed adjacent to the first deep portion and extending vertically through the insulating layer, such that a level of a bottom surface of the first shallow portion is located above a level of a directly opposite first region of an upper portion of the second semiconductor structure, wherein the first shallow portion protrudes from the first deep portion in a second horizontal direction towards the first region of the second semiconductor structure and to a horizontal position disposed at least halfway between the first semiconductor structure and the second semiconductor structure;

forming a first set of source/drain contacts in the first set of source/dram contact openings, wherein forming the first set of source/drain contacts comprises forming a first source/drain contact in the first source/drain contact opening, wherein the first source/drain contact includes: (i) a first vertically extending contact portion arranged in the first deep portion and (ii) a first via landing portion arranged in the first shallow portion and protruding horizontally from the first vertically extending contact portion;

forming, in the insulating layer, a second set of source/strain contact openings above a second set of regions of the upper portion of the second semiconductor structure;

subsequent to forming the second set of source/drain contact openings, forming a contact spacer layer on one or more sidewalls of the second set of source/drain contact openings;

subsequent to forming the contact spacer layer, forming a second set of source/drain contacts in the second set of source/drain contact openings; and

forming an interconnection level, the interconnection level including a first vertical via abutting the first via landing portion.

12. The method according to claim 11 , wherein a set of gate structures extends across the first semiconductor structure and the second semiconductor structure, wherein the set of gate structures are embedded by the insulating layer, and wherein each of the regions of the first semiconductor structure and the second semiconductor structure is a region formed adjacent to at least one gate structure of the set of gate structures.

13. The method according to claim 12 , wherein the first, region of the first set of regions of the first semiconductor structure and the first region of the second set of regions of the second semiconductor structure are formed on a first side of a first gate structure of the set of gate structures, and wherein a second region of the first set of regions of the first semiconductor structure and a second region of the second set of regions of the second semiconductor structure are formed on a second side of the first gate structure, opposite the first side.

14. The method according claim 12 , wherein the set of gate structures and the first set of regions of the first semiconductor structure are covered by a first spacer layer, wherein the first set of source/drain contact openings exposes portions of the first spacer layer that cover the first set of regions, and wherein the method further comprises removing the portions of the first spacer layer prior to forming the first set of source/drain contacts.

15. The method according to claim 12 , wherein the set of gate structures and the second set of regions of the second semiconductor structure are covered by a first spacer layer, wherein the second set of source/drain contact openings exposes (i) portions of the first spacer layer that cover the second set of regions and (ii) portions of the first spacer layer that cover one or more sidewalls of the set of gate structures, wherein the method further comprises:

removing the portions of the first spacer layer from the second set of regions and from the one or more sidewalls of the set of gate structures, wherein the one or more sidewalls of the set of gate structures form exposed sidewalls of the second set of source/drain contact openings; and thereafter

after removing the portions of the first spacer layer, forming a contact spacer layer on the exposed sidewalls of the second set of source/drain contact openings.

16. The method according to claim 12 , wherein the set of gate structures forms a set of sacrificial gate structures, and wherein the method further comprises replacing the set of sacrificial gate structures with a set of replacement gate structures subsequent to forming the second set of source/drain contacts and prior to forming the interconnection level.

17. The method according to claim 11 , further comprising:

subsequent to forming the second set of source/drain contact openings and prior to forming the second set of source/drain contacts, epitaxially growing a respective doped semiconductor top portion in each region of the second set of regions of the second semiconductor structure, wherein the level of the bottom surface of the first shallow portion of the first source/drain contact opening is located above a level of the doped semiconductor top portion on the first region of the second set of regions of the second semiconductor structure.

18. The method according to claim 11 , further comprising:

subsequent to forming the first set of source/drain contact openings and prior to forming the first set of source/drain contacts, epitaxially growing a respective doped semiconductor top portion in each region of the first set of regions.

19. The method according to claim 11 , wherein forming the first set of source/drain contacts comprises depositing a contact material in the first set of source/drain openings, and wherein the method further comprises forming a capping layer on the first set of source/drain contacts.

20. The method according to claim 11 , wherein the first semiconductor structure and the second semiconductor structure form part of a functional cell, wherein forming the interconnection level comprises forming the interconnection level to include a middle routing track extending in the first horizontal direction and arranged at a horizontal position halfway between the first and second semiconductor structures, and wherein the middle routing track abuts the first vertical via.