Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height

1. A nanowire device, comprising:

a nanowire disposed on a substrate, wherein a longitudinal length of the nanowire comprises:

an undoped channel region of a first semiconductor material;

an undoped semiconductor source region electrically coupled with a first end of the channel region;

an undoped semiconductor drain region electrically coupled with a second end of the channel region;

a gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around the channel region;

a source stack electrically isolated from the gate conductor, coaxially wrapping completely around the semiconductor source region and extending along at least a portion of the semiconductor source region; and

a drain stack electrically isolated from the gate conductor, coaxially wrapping completely around the semiconductor drain region and extending along at least a portion of the semiconductor drain region;

wherein the source stack comprises a source conductor contacting the semiconductor source region and extending along at least a portion of the semiconductor source region, the source conductor comprising a degenerately doped n-type semiconductor and there is an offset in conduction band energy between the degenerately doped n-type semiconductor and the semiconductor source region such that a conduction band minimum in the degenerately doped n-type semiconductor is at a higher energy than a conduction band minimum in the semiconductor source region.

2. The nanowire device of claim 1 wherein the semiconductor source region comprises silicon and the degenerately doped n-type semiconductor comprises degenerately doped n-type gallium phosphide.

3. The nanowire device of claim 1 wherein the degenerately doped n-type semiconductor comprises degenerately doped n-type gallium phosphide.

4. The nanowire device of claim 1 wherein the degenerately doped n-type semiconductor comprises Ge.

5. The nanowire device of claim 1 wherein the degenerately doped n-type semiconductor comprises AlAs.

6. The nanowire device of claim 1 wherein the degenerately doped n-type semiconductor comprises AlSb.

7. The nanowire device of claim 1 wherein the degenerately doped n-type semiconductor comprises ZnS.

8. The nanowire device of claim 1 wherein the degenerately doped n-type semiconductor comprises ZnSe.

9. The nanowire device of claim 1 wherein the degenerately doped n-type semiconductor comprises ZnTe.

10. A nanowire device, comprising:

a nanowire disposed on a substrate, wherein a longitudinal length of the nanowire comprises:

an undoped channel region of a first semiconductor material;

an undoped semiconductor source region electrically coupled with a first end of the channel region;

an undoped semiconductor drain region electrically coupled with a second end of the channel region;

a gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around the channel region;

a source stack electrically isolated from the gate conductor, coaxially wrapping completely around the semiconductor source region and extending along at least a portion of the semiconductor source region; and

a drain stack electrically isolated from the gate conductor, coaxially wrapping completely around the semiconductor drain region and extending along at least a portion of the semiconductor drain region;

wherein the source stack comprises a source conductor contacting an interfacial layer disposed over the semiconductor source region, the interfacial layer including at least one epitaxial bilayer of group III and group V atomic monolayers.

11. The nanowire device of claim 10 , wherein the source conductor comprises a degenerately doped n-type semiconductor, wherein the monolayer of group V atoms is adjacent to and in contact with the source region, the source region comprises a group IV semiconductor source region, and the monolayer of group III atoms is adjacent to and in contact with the degenerately n-type doped semiconductor.

12. The nanowire device of claim 11 , wherein the group IV semiconductor and the degenerately doped n-type semiconductor comprise different semiconductor materials.

13. The nanowire device of claim 11 , wherein the group IV semiconductor and the degenerately doped n-type semiconductor each comprise a same semiconductor material.

14. The nanowire device of claim 11 , wherein the interfacial layer comprises a monolayer of gallium (Ga) atoms and a monolayer of arsenic (As) atoms, and the group IV semiconductor and the degenerately doped n-type semiconductor each comprise germanium (Ge).

15. The nanowire device of claim 10 , wherein the source conductor comprises a degenerately doped p-type semiconductor, wherein the monolayer of group V atoms is adjacent to and in contact with the degenerately doped p-type semiconductor, the source region comprises a group IV semiconductor source region, and the monolayer of group III atoms is adjacent to and in contact with the group IV semiconductor.

16. The nanowire device of claim 15 , wherein the group IV semiconductor and the degenerately doped p-type semiconductor comprise different semiconductor materials.

17. The nanowire device of claim 16 , wherein the interfacial layer comprises a monolayer of gallium (Ga) atoms and a monolayer of arsenic (As) atoms, and the group IV semiconductor and the degenerately doped p-type semiconductor each comprise germanium (Ge).

18. The nanowire device of claim 15 , wherein the group IV semiconductor and the degenerately doped p-type semiconductor each comprise a same semiconductor material.

19. A nanowire device, comprising:

a nanowire disposed on a substrate, wherein a longitudinal length of the nanowire comprises:

an undoped channel region of a first semiconductor material;

an undoped semiconductor source region electrically coupled with a first end of the channel region;

an undoped semiconductor drain region electrically coupled with a second end of the channel region;

a gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around the channel region;

a source stack electrically isolated from the gate conductor, coaxially wrapping completely around the semiconductor source region and extending along at least a portion of the semiconductor source region; and

a drain stack electrically isolated from the gate conductor, coaxially wrapping completely around the semiconductor drain region and extending along at least a portion of the semiconductor drain region;

wherein the source stack comprises a source conductor contacting the semiconductor source region and extending along at least a portion of the semiconductor source region, the source conductor comprising a degenerately p-type doped semiconductor and there is an offset in valence band energy between the degenerately doped p-type semiconductor and the semiconductor source region such that a valence band maximum in the degenerately doped p-type semiconductor is at a lower energy than a valence band maximum in the semiconductor source region.

20. The nanowire device of claim 19 wherein the semiconductor source region comprises germanium and the degenerately doped p-type semiconductor comprises degenerately doped p-type silicon germanium.

21. A nanowire transistor, comprising:

a nanowire disposed on a substrate, wherein a longitudinal length of the nanowire comprises:

an undoped channel region of a first semiconductor material;

an undoped semiconductor source region electrically coupled with a first end of the channel region;

an undoped semiconductor drain region electrically coupled with a second end of the channel region;

a gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around the channel region;

a source stack comprising an interfacial layer and a source conductor, which is electrically isolated from the gate conductor, coaxially wrapping completely around the semiconductor source region and extending along at least a portion of the semiconductor source region; and

a drain stack comprising an interfacial layer and a drain conductor, which is electrically isolated from the gate conductor, coaxially wrapping completely around the semiconductor drain region and extending along at least a portion of the semiconductor drain region;

wherein a Schottky barrier between the source conductor and the semiconductor source region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor source region.

22. The nanowire transistor of claim 21 , wherein a Schottky barrier between the drain conductor and the semiconductor drain region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor drain region.

23. The nanowire transistor of claim 21 , wherein the nanowire is 20 nm or less thick.

24. The nanowire transistor of claim 21 , wherein the free charge carriers are electrons.

25. The nanowire transistor of claim 21 , wherein the free charge carriers are holes.

26. The nanowire transistor of claim 21 , wherein the Schottky barrier between the source conductor and the semiconductor source region is between −0.1 eV and −0.5 eV.

27. The nanowire transistor of claim 21 , wherein the interfacial layer of the source stack and interfacial layer of the drain stack each comprise a material that would be is an insulator or a semiconductor in its bulk state.

28. The nanowire transistor of claim 21 , wherein the semiconductor channel, the semiconductor source region, and the semiconductor drain region are all comprised of the same semiconductor material.

29. The nanowire transistor of claim 21 , wherein the semiconductor channel and the semiconductor source region, and the semiconductor drain region are not all comprised of the same semiconductor material.

30. The nanowire transistor of claim 21 , wherein the semiconductor source region comprises silicon, germanium, silicon carbide, or an alloy comprising two or more of silicon, germanium, carbon and tin.

31. The nanowire transistor of claim 30 , wherein the free charge carriers are electrons.

32. The nanowire transistor of claim 31 , wherein the interfacial layer of the source stack comprises a monolayer of elements from group V or group VI.

33. The nanowire transistor of claim 30 , wherein the free charge carriers are holes.

34. The nanowire transistor of claim 33 , wherein the interfacial layer of the source stack comprises a monolayer of elements from group III or group II.