Circuits with low-pass filters and differential amplifiers
A circuit comprises a first set of serially-connected inverters comprising an input port, the first set of serially-connected inverters comprising a first subset of serially-connected inverters, the first subset of serially-connected inverters odd in number and comprising an input port and an output port; a first low-pass filter comprising an input port coupled to the output port of the first subset of serially-connected inverters, and an output port; a second low-pass filter comprising an input port coupled to the input port of the first subset of serially-connected inverters, and an output port; and a first differential amplifier comprising a first input port coupled to output port of the first low-pass filter, a second input port coupled to the output port of the second low-pass filter, and an output port coupled to the input port of the first set of serially-connected inverters.
1. A circuit comprising:
a first clock signal input port;
a first inverter having an input port coupled to the first clock signal input port, and an output port;
a second inverter having an input port coupled to the output port of the first inverter, and an output port;
a third inverter having an input port coupled to the output port of the second inverter, and an output port;
a fourth inverter having an input port coupled to the output port of the third inverter, and an output port;
a first low-pass filter having an input port coupled to the output port of the third inverter, and an output port;
a second low-pass filter having an input port coupled to the output port of the fourth inverter, and an output port; and
a first differential amplifier having a first input port coupled to the output port of the first low-pass filter, a second input port coupled to the output port of the second low-pass filter, an output port coupled to the input port of the first inverter, and a capacitor having a first terminal connected to the first input port and a second terminal connected to the output port.
2. The circuit of claim 1 , further comprising:
a second clock signal input port;
a fifth inverter having an input port coupled to the second clock signal input port, and an output port;
a first pair of cross-coupled inverters coupled to the output port of the first inverter and to the output port of the fifth inverter;
a sixth inverter having an input port coupled to the output port of the fifth inverter, and an output port;
a second pair of cross-coupled inverters coupled to the output port of the second inverter and to the output port of the sixth inverter;
a seventh inverter having an input port coupled to the output port of the sixth inverter, and an output port;
a third pair of cross-coupled inverters coupled to the output port of the third inverter and to the output port of the seventh inverter;
an eighth inverter having an input port coupled to the output port of the seventh inverter, and an output port;
a third low-pass filter having an input port coupled to the output port of the seventh inverter, and an output port;
a fourth low-pass filter having an input port coupled to the output port of the eighth inverter, and an output port; and
a second differential amplifier having a first input port coupled to the output port of the third low-pass filter, a second input port coupled to the output port of the fourth low-pass filter, an output port coupled to the input port of the fifth inverter, and a second capacitor having a first terminal connected to the first input port and a second terminal connected to the output port.