Parallel-connected merged-floating-gate nFET-pFET EEPROM cell and array
View Patent ↗A shared floating gate device, the device including an nFET, a pFET including a different material than that of the nFET, and a floating gate.
1. A device, comprising:
an nFET;
a pFET; and
a parallel-connected merged floating gate.
2. The device of claim 1 , wherein the nFET and the pFET share the floating gate to form an electrically erasable and programmable non-volatile memory device.
3. The device of claim 1 , wherein the nFET includes an nFET gate dielectric,
wherein the pFET includes a pFET gale dielectric, and
wherein the pFET gate dielectric and the nFET dielectric comprise different materials.
4. The device of claim 3 , wherein the different materials are selected so that a difference of energy barriers for a hot-carrier injection formed by the nFET gate dielectric and the pFET gate dielectric is 1 eV or less.
5. The device of claim 1 , wherein the nFET comprises one of:
Y 2 O 3 ;
ZrO 2 ; and
HfO 2 .
6. The device of claim 1 , wherein the pFET comprises one of:
Si 3 N 4 ;
Y 2 O 3 ;
ZrO 2 ; and
HfO 2 .
7. An electrically erasable programmable read-only memory (EEPROM) cell, the cell comprising:
an nFET;
a pFET; and
a parallel-connected merged floating gate.
8. The cell of claim 7 , wherein the nFET and the pFET share the floating gate to form an electrically programmable and erasable non-volatile memory device.
9. The cell of claim 7 , wherein the nFET includes an nFET gate dielectric,
wherein the pFET includes a pFET gate dielectric, and
wherein the pFET gate dielectric and the nFET dielectric comprise different materials.
10. The cell of claim 9 , wherein the different materials are selected so that a difference of energy barriers for a hot-carrier injection formed by the nFET gate dielectric and pFET gate dielectric is 1 eV or less.
11. The cell of claim 7 , wherein the nFET comprises one of:
Y 2 O 3 ;
ZrO 2 ; and
HfO 2 .
12. The cell of claim 7 , wherein the pFET comprises one of:
Si 3 N 4 ;
Y 2 O 3 ;
ZrO 2 ; and
HfO 2 .
13. An array structure, comprising:
a plurality of cells, each cell including:
an nFET;
a pFET;
a floating gate; and
an nFET access transistor including a drain connected to a source of the nFET and a drain of the pFET.
14. The array structure of claim 13 , further comprising one nFET access transistor per word-line.
15. The array structure of claim 13 , further comprising one bit-line per pFET access transistor.
16. The array structure of claim 13 , further comprising a word-line and two bit-lines per each cell, said word-line being connected to the gate of the access transistor, one of said bit-lines being connected to the source of the pFET and the other one of said bit-lines being connected to the drain of nFET.
17. The array structure of claim 13 , further comprising peripheral logic circuits,
wherein the plurality of cells and the peripheral logic circuits are built on a same substrate.
18. The array structure of claim 13 , further comprising peripheral logic circuits,
wherein the plurality of cells is built on a polycrystalline silicon film-on-insulator and the peripheral logic circuits are built on a bulk silicon substrate.
19. The array structure of claim 13 , further comprising peripheral logic circuits,
wherein the plurality of cells and the peripheral logic circuits are built on a same bulk silicon substrate.
20. The array structure of claim 13 , wherein each of the plurality of cells includes one access transistor per wordline.