Three-dimensional memory device including liner free molybdenum word lines and methods of making the same
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing molybdenum portions located over a substrate, memory stack structures extending through the alternating stack, and including a memory film and a vertical semiconductor channel, and a backside blocking dielectric layer of a dielectric oxide material including aluminum atoms and at least one of lanthanum or zirconium atoms which directly contacts the molybdenum portions.
1. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate, wherein the electrically conductive layers comprise molybdenum portions;
memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel; and
a backside blocking dielectric layer comprising a dielectric oxide material including aluminum atoms and at least one of lanthanum or zirconium atoms, wherein the backside blocking dielectric layer is located between the electrically conductive layers and the memory stack structures and directly contacts the molybdenum portions,
wherein each memory film comprises a tunneling dielectric, a charge storage layer, and a front side silicon oxide blocking dielectric layer which directly contacts the backside blocking dielectric layer, and further comprising an additional feature comprising:
a first feature wherein the backside blocking dielectric includes aluminum oxide and at least one of lanthanum oxide or zirconium oxide which mitigates a dipole between the aluminum oxide and the front side silicon oxide blocking dielectric; or
a second feature wherein the backside blocking dielectric layer comprises a layer stack of an aluminum oxide layer and a lanthanum oxide layer, wherein the lanthanum oxide layer is in direct contact with the front side silicon oxide blocking dielectric layer and the aluminum oxide layer is in direct contact with the molybdenum portions; or
a third feature wherein the backside blocking dielectric layer comprises a layer stack of an aluminum oxide layer and a zirconium oxide layer, wherein the zirconium oxide layer is in direct contact with the front side silicon oxide blocking dielectric layer and the aluminum oxide layer is in direct contact with the molybdenum portions; or
a fourth feature wherein the backside blocking dielectric layer comprises an aluminum lanthanum oxide layer in direct contact with the molybdenum portions; or
a fifth feature wherein the backside blocking dielectric layer comprises an aluminum zirconium oxide layer in direct contact with the molybdenum portions.
2. The three-dimensional memory device of Claim 1 , wherein the additional feature is the first feature.
3. The three-dimensional memory device of Claim 1 , wherein the additional feature is the second feature.
4. The three-dimensional memory device of Claim 1 , wherein the additional feature is the third feature.
5. The three-dimensional memory device of Claim 1 , wherein the additional feature is the fourth feature.
6. The three-dimensional memory device of Claim 1 , wherein the additional feature is the fifth feature.
7. The three-dimensional memory device of claim 1 , wherein each of the electrically conductive layers comprise word lines which consist of only a respective one of the molybdenum portions.
8. The three-dimensional memory device of claim 1 , further comprising:
a backside trench vertically extending through each level of the alternating stack and extending to a top surface of the substrate; and
a dielectric wall structure located in the backside trench, wherein each of the molybdenum portions directly contacts a respective portion of a sidewall of the dielectric wall structure.
9. The three-dimensional memory device of claim 1 , wherein no electrically conductive diffusion barrier is present between the molybdenum portions and the backside blocking dielectric layer.
10. The three-dimensional memory device of claim 1 , wherein:
the backside blocking dielectric layer is located between the electrically conductive layers and a combination of the insulating layers and the memory stack structures; and
the molybdenum portions are vertically spaced from the insulating layers by horizontal portions of the backside blocking dielectric layer, and laterally spaced from the memory stack structures by vertical portions of the backside blocking dielectric layer.
11. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
the semiconductor substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;
the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.
12. A method of forming a three-dimensional memory device, comprising:
forming an alternating stack of insulating layers and spacer material layers over a substrate;
forming memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel;
forming backside recesses by removing the sacrificial material layers selective to the insulating layers and the memory stack structures;
forming a backside blocking dielectric layer comprising a dielectric oxide material including aluminum atoms and at least one of lanthanum or zirconium atoms directly on surfaces of the insulating layers and the memory stack structures in the backside recesses; and
forming electrically conductive layers including molybdenum portions by depositing the molybdenum portions directly on surfaces of the backside blocking dielectric layer in remaining volumes of the backside recesses,
wherein each memory film comprises a tunneling dielectric, a charge storage layer, and a front side silicon oxide blocking dielectric layer which directly contacts the backside blocking dielectric layer, and further comprising an additional feature comprising:
a first feature wherein the backside blocking dielectric includes aluminum oxide and at least one of lanthanum oxide or zirconium oxide which mitigate a dipole between the aluminum oxide and the front side silicon oxide blocking dielectric; or
a second feature wherein the backside blocking dielectric layer comprises a layer stack of an aluminum oxide layer and a lanthanum oxide layer, wherein the lanthanum oxide layer is in direct contact with the front side silicon oxide blocking dielectric layer and the aluminum oxide layer is in direct contact with the molybdenum portions; or
a third feature wherein the backside blocking dielectric layer comprises a layer stack of an aluminum oxide layer and a zirconium oxide layer, wherein the zirconium oxide layer is in direct contact with the front side silicon oxide blocking dielectric layer and the aluminum oxide layer is in direct contact with the molybdenum portions; or
a fourth feature wherein the backside blocking dielectric layer comprises an aluminum lanthanum oxide layer in direct contact with the molybdenum portions; or
a fifth feature wherein the backside blocking dielectric layer comprises an aluminum zirconium oxide layer in direct contact with the molybdenum portions.
13. The method of claim 12 , wherein:
the molybdenum portions are formed by a conformal deposition process that deposits material portions consisting essentially of molybdenum; and
all volumes of the backside recesses are partially or completely filled with the backside blocking dielectric layer and the molybdenum portions.
14. The method of Claim 12 , wherein the additional feature is the first feature.
15. The method of Claim 12 , wherein the additional feature is the second feature.
16. The method of Claim 12 , wherein the additional feature is the third feature.
17. The method of Claim 12 , wherein the additional feature is the fourth feature.
18. The method of Claim 12 , wherein the additional feature is the fifth feature.