Formation of air gap spacers for reducing parasitic capacitance
A method is presented for reducing parasitic capacitance. The method includes forming a source region and a drain region within a substrate, forming spacers in direct contact with sidewalls of a sacrificial layer, depositing an inter-layer dielectric (ILD) over the source and drain regions, replacing the sacrificial layer with a gate structure, removing the ILD, and depositing a sacrificial dielectric layer. The method further includes removing portions of the sacrificial dielectric layer to expose top surfaces of the source and drain regions, depositing a conductive material over the exposed top surfaces of the source and drain regions, and removing remaining portions of the sacrificial dielectric layer to form air gap spacers between the gate structure and the source and drain regions.
1. A method for reducing parasitic capacitance, the method comprising:
forming a source region and a drain region within a substrate;
forming spacers in direct contact with the source and drain regions, and the substrate;
depositing an inter-layer dielectric (ILD) over the source and drain regions;
forming a gate structure adjacent the spacers;
removing the ILD and the spacers;
depositing a sacrificial dielectric layer in direct contact with the source and drain regions;
removing portions of the sacrificial dielectric layer to expose top surfaces of the source and drain regions and to define remaining portions of the sacrificial dielectric layer;
depositing a conductive material over the exposed top surfaces of the source and drain regions;
removing the remaining portions of the sacrificial dielectric layer to form trenches on opposed ends of the conductive material;
depositing a dielectric liner; and
depositing an oxide within the trenches to form air gap spacers between the gate structure and the conductive material.
2. The method of claim 1 , wherein the sacrificial dielectric layer includes germanium dioxide (GeO 2 ).
3. The method of claim 1 , wherein each of the air gap spacers extends along a length of the conductive material.
4. The method of claim 1 , wherein the air gap spacers extend from a top surface of the substrate to a top surface of the conductive material.
5. The method of claim 1 , wherein the air gap spacers are encapsulated by a single material.
6. The method of claim 1 , wherein the air gaps spacers are encapsulated by the dielectric liner.
7. The method of claim 1 , wherein air gaps in the air gap spacers have a substantially oval-shaped configuration.
8. The method of claim 1 , wherein the remaining portions of the sacrificial dielectric layer are removed by employing deionized (DI) water.
9. A method for reducing parasitic capacitance, the method comprising:
depositing a sacrificial dielectric layer in direct contact with source and drain regions;
removing portions of the sacrificial dielectric layer to expose top surfaces of the source and drain regions and to define remaining portions of the sacrificial dielectric layer;
depositing a conductive material over the exposed top surfaces of the source and drain regions;
removing the remaining portions of the sacrificial dielectric layer to form trenches on opposed ends of the conductive material;
depositing a dielectric liner; and
depositing an oxide within the trenches to form air gap spacers between the gate structure and the conductive material.
10. The method of claim 9 , wherein the source and drain regions are formed within a substrate.
11. The method of claim 10 , wherein spacers are formed in direct contact with the source and drain regions, and the substrate.
12. The method of claim 11 , wherein a gate structure is formed adjacent the spacers.
13. The method of claim 12 , wherein the spacers are removed before depositing the sacrificial dielectric layer.
14. The method of claim 9 , wherein the sacrificial dielectric layer includes germanium dioxide (GeO 2 ).
15. The method of claim 9 , wherein each of the air gap spacers extends along a length of the conductive material.
16. The method of claim 9 , wherein the air gap spacers extend from a top surface of a substrate to a top surface of the conductive material.
17. The method of claim 9 , wherein the air gaps spacers are encapsulated by the dielectric liner.
18. The method of claim 9 , wherein air gaps in the air gap spacers have a substantially oval-shaped configuration.
19. The method of claim 9 , wherein the remaining portions of the sacrificial dielectric layer are removed by employing deionized (DI) water.
20. The method of claim 9 , wherein the dielectric liner includes silicon nitride (SiN).