Via structure and methods thereof

1. A method, comprising:

providing a substrate, wherein the substrate includes a conductive feature in a top portion of the substrate;

forming a buffer layer over the substrate;

forming a dielectric layer over the buffer layer;

performing a first etching process to form an opening in the dielectric layer, thereby exposing a top surface of the buffer layer; and

performing a second etching process to extend the opening downwardly into the buffer layer, thereby exposing a top surface of the conductive feature, wherein the performing of the second etching process includes laterally enlarging a footing profile of the opening

wherein the performing of the first etching process forms sidewalls of the opening tapered inwardly towards a center of the opening, and the performing of the second etching process extends the sidewalls of the opening outwardly away from the center of the opening.

2. The method of claim 1 , further comprising:

filling the opening with a conductive material, such that the conductive material is in physical contact with the top surface of the conductive feature.

3. The method of claim 1 , wherein the first etching process includes an anisotropic etching and the second etching process includes an isotropic etching or a lateral etching.

4. The method of claim 1 , wherein the first etching process includes a reactive ion etching and the second etching process includes a wet etching.

5. The method of claim 1 , wherein the forming of the buffer layer includes forming at least a top sub-layer and a bottom sub-layer of different material compositions, and the second etching process includes an anisotropic etching to extend the opening downwardly through the top sub-layer followed by an isotropic etching or a lateral etching to laterally enlarge the footing profile of the opening in the bottom sub-layer.

6. The method of claim 5 , wherein the forming of the buffer layer further includes forming a middle sub-layer sandwiched by the top and bottom sub-layers.

7. The method of claim 1 , wherein the performing of the second etching process forms a rounded corner at a bottom portion of the opening.

8. The method of claim 1 , wherein after the performing of the second etching process, a cross section of the opening that has a smallest cross-sectional area is located below the top surface of the buffer layer and above the top surface of the conductive feature.

9. The method of claim 1 , wherein after the performing of the second etching process, a cross section of the opening that has a smallest cross-sectional area is coplanar with the top surface of the buffer layer.

10. The method of claim 1 , wherein after the performing of the second etching process, the opening has a bottom surface larger than a top surface.

11. A method of forming a semiconductor device, comprising:

forming a first etch stop layer over a substrate;

forming a second etch stop layer over the first etch stop layer, wherein the second and first etch stop layers include different material compositions;

forming a low-k dielectric layer over the second etch stop layer; and

forming a via extending through the low-k dielectric layer, the second etch stop layer, and the first etch stop layer, wherein the via has a top sidewall tapered inwardly towards a center of the via and a bottom sidewall tapered outwardly away from the center of the via, wherein the top sidewall and the bottom sidewall intersect below a top surface of the second etch stop layer.

12. The method of claim 11 , wherein the top sidewall and the bottom sidewall intersect at a top surface of the first etch stop layer.

13. The method of claim 11 , wherein each of the first and second etch stop layers is an aluminum-containing layer.

14. The method of claim 13 , further comprising:

forming a silicon carbide layer between the first and second etch stop layers.

15. The method of claim 11 , wherein the forming of the via includes:

etching the low-k dielectric layer, thereby forming a via hole;

etching the second etch stop layer, thereby extending the via hole downwardly through the second etch stop layer;

etching the first etch stop layer, thereby laterally enlarging a bottom portion of the via hole in the first etch stop layer; and

filling the via hole with a conductive material.

16. The method of claim 15 , wherein each of the etching of the low-k dielectric layer and the etching of the second etch stop layer includes an anisotropic etching, and wherein the etching of the first etch stop layer includes an isotropic etching or a lateral etching.

17. A method of fabricating an integrated circuit, comprising:

depositing a buffer layer over a substrate;

depositing a dielectric layer over the buffer layer;

removing a portion of the dielectric layer to form an opening;

etching the buffer layer through the opening, thereby extending the opening through the buffer layer and exposing a top surface of the substrate in the opening, wherein the etching of the buffer layer includes an isotropic etching or a lateral etching, and wherein after the etching of the buffer layer, a cross section of the opening that has a smallest cross-sectional area is located below a top surface of the buffer layer and above the top surface of the substrate; and

filling the opening with a conductive feature.

18. The method of claim 17 , wherein after the etching of the buffer layer, the opening has a bottom area that is larger than a cross-sectional area of a portion of the opening surrounded by the dielectric layer.

19. The method of claim 17 , wherein the conductive feature includes a barrier layer covering sidewalls of the opening and a conductive layer over the barrier layer.

20. The method of claim 17 , wherein the depositing of the buffer layer includes depositing a bottom sub-layer over the substrate and depositing a top sub-layer over the bottom sub-layer, wherein the bottom and top sub-layers include different material compositions.