IP Library › Granted Patent US 10,868,009
Granted Patent B2
US 10,868,009 · App. 16/809,046 · Granted Dec 15, 2020

Semiconductor device and manufacturing method thereof

Inventors: Winnie Victoria Wei-Ning Chen (Zhubei, TW); Meng-Hsuan Hsiao (Hsinchu, TW); Tung-Ying Lee (Hsinchu, TW); Pang-Yen Tsai (Jhu-bei, TW); Yasutoshi Okuno (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L27/092H01L21/02636H01L21/30625H01L21/823807H01L29/0673H01L29/0676H01L29/1033H01L29/16H01L29/42392
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Quick Facts
Patent No.
US 10,868,009
App. No.
16/809,046
Granted
Dec 15, 2020
Kind
B2
Abstract

A method for forming a semiconductor device is provided. The method includes forming a first recess in a substrate. The method includes forming a first semiconductor layer into the first recess. The first semiconductor layer and the substrate are made of different materials, and a first top surface of the first semiconductor layer is lower than a second top surface of the substrate. The method includes forming a second semiconductor layer over the first top surface and the second top surface, wherein a third top surface of the second semiconductor layer over the first top surface is substantially level with the second top surface of the substrate, and the second semiconductor layer and the substrate are made of different materials. The method includes forming a third semiconductor layer over the second semiconductor layer. The third semiconductor layer and the second semiconductor layer are made of different materials.

Claims (47)

1. A method for forming a semiconductor device, comprising:

forming a first recess in a substrate;

forming a first semiconductor layer into the first recess, wherein the first semiconductor layer and the substrate are made of different materials, and a first top surface of the first semiconductor layer is lower than a second top surface of the substrate;

forming a second semiconductor layer over the first top surface and the second top surface, wherein a third top surface of the second semiconductor layer over the first top surface is substantially level with the second top surface of the substrate, and the second semiconductor layer and the substrate are made of different materials; and

forming a third semiconductor layer over the second semiconductor layer, wherein the third semiconductor layer and the second semiconductor layer are made of different materials.

2. The method for forming the semiconductor device as claimed in claim 1 , wherein a height difference between the first top surface and the second top surface is substantially equal to a thickness of the second semiconductor layer over the first top surface of the first semiconductor layer.

3. The method for forming the semiconductor device as claimed in claim 1 , wherein the second semiconductor layer conformally covers the first top surface and the second top surface, and the third semiconductor layer conformally covers the second semiconductor layer.

4. The method for forming the semiconductor device as claimed in claim 1 , wherein the first semiconductor layer and the second semiconductor layer are made of a same first material.

5. The method for forming the semiconductor device as claimed in claim 4 , wherein the substrate and the third semiconductor layer are made of a same second material.

6. The method for forming the semiconductor device as claimed in claim 5 , wherein the first material comprises silicon germanium, and the second material comprises silicon.

7. The method for forming the semiconductor device as claimed in claim 1 , further comprising:

partially removing the third semiconductor layer, the second semiconductor layer, the first semiconductor layer, and the substrate to form second recesses in the third semiconductor layer, the second semiconductor layer, the first semiconductor layer, and the substrate, wherein the second recesses pass through the third semiconductor layer and the second semiconductor layer and extend into the first semiconductor layer and the substrate,

a first fin element and a second fin element are between the second recesses, the first fin element comprises a first portion of the substrate, a second portion of the second semiconductor layer, and a third portion of the third semiconductor layer, and the second fin element comprises a fourth portion of the first semiconductor layer, a fifth portion of the second semiconductor layer, and a sixth portion of the third semiconductor layer.

8. The method for forming the semiconductor device as claimed in claim 7 , further comprising:

forming an isolation structure in the second recesses, wherein a fourth top surface of the isolation structure is lower than the first top surface of the first semiconductor layer.

9. The method for forming the semiconductor device as claimed in claim 8 , further comprising:

removing the first portion of the substrate outside of the isolation structure, the third portion of the third semiconductor layer, the fourth portion of the first semiconductor layer outside of the isolation structure, and the fifth portion of the second semiconductor layer.

10. The method for forming the semiconductor device as claimed in claim 9 , further comprising:

forming a first gate stack over the substrate and the isolation structure and surrounding the second portion of the second semiconductor layer; and

forming a second gate stack over the first semiconductor layer and the isolation structure and surrounding the sixth portion of the third semiconductor layer.

11. A method for forming a semiconductor device, comprising:

forming a first recess in a substrate;

forming a first semiconductor layer into the first recess, wherein the first semiconductor layer and the substrate are made of different materials, and a first top surface of the first semiconductor layer is higher than a second top surface of the substrate;

forming a second semiconductor layer over the first top surface and the second top surface, wherein a third top surface of the second semiconductor layer over the second top surface is substantially level with the first top surface of the first semiconductor layer, and the second semiconductor layer and the substrate are made of different materials; and

forming a third semiconductor layer over the second semiconductor layer, wherein the third semiconductor layer and the second semiconductor layer are made of different materials.

12. The method for forming the semiconductor device as claimed in claim 11 , further comprising:

partially removing the third semiconductor layer, the second semiconductor layer, the first semiconductor layer, and the substrate to form second recesses in the third semiconductor layer, the second semiconductor layer, the first semiconductor layer, and the substrate, wherein the second recesses pass through the third semiconductor layer and the second semiconductor layer and extend into the first semiconductor layer and the substrate,

a first fin element and a second fin element are between the second recesses, the first fin element comprises a first portion of the substrate, a second portion of the second semiconductor layer, and a third portion of the third semiconductor layer, and the second fin element comprises a fourth portion of the first semiconductor layer, a fifth portion of the second semiconductor layer, and a sixth portion of the third semiconductor layer.

13. The method for forming the semiconductor device as claimed in claim 12 , further comprising:

forming an isolation structure in the second recesses, wherein a fourth top surface of the isolation structure is lower than the first top surface of the first semiconductor layer.

14. The method for forming the semiconductor device as claimed in claim 13 , further comprising:

removing the third portion of the third semiconductor layer, the fourth portion of the first semiconductor layer outside of the isolation structure, and the fifth portion of the second semiconductor layer.

15. The method for forming the semiconductor device as claimed in claim 14 , further comprising:

forming a first gate stack over the substrate and the isolation structure and wrapping the second portion of the second semiconductor layer; and

forming a second gate stack over the first semiconductor layer and the isolation structure and wrapping the sixth portion of the third semiconductor layer.

16. A semiconductor device, comprising:

a substrate comprising a first base portion and a first fin portion over the first base portion;

a semiconductor layer partially embedded in the substrate, wherein the semiconductor layer comprises a second base portion and a second fin portion over the second base portion, a first top surface of the first fin portion is substantially coplanar with a second top surface of the second fin portion, and the semiconductor layer and the substrate are made of different materials;

a first strip structure over the first fin portion, wherein the first strip structure and the substrate are made of different materials;

a second strip structure over the second fin portion, wherein the second strip structure and the semiconductor layer are made of different materials;

a first gate stack over the substrate and surrounding the first strip structure; and

a second gate stack over the semiconductor layer and surrounding the second strip structure.

17. The semiconductor device as claimed in claim 16 , wherein the first strip structure and the second strip structure are made of different materials.

18. The semiconductor device as claimed in claim 16 , wherein a third top surface of the first strip structure and a fourth top surface of the second strip structure are substantially coplanar.

19. The semiconductor device as claimed in claim 16 , further comprising:

an isolation structure between the first fin portion and the second fin portion and over the first base portion and the second base portion.

20. The semiconductor device as claimed in claim 19 , wherein a third top surface of the isolation structure, the first top surface of the first fin portion, and the second top surface of the second fin portion are substantially coplanar.

Continuity (3)
Continuation 15963920 · Apr 26, 2018
Provisional Application 62593143 · Nov 30, 2017
Related Publication 20200203342A1 · Jun 25, 2020