Semiconductor memory devices

1. A semiconductor memory device, comprising:

a semiconductor substrate including an active region defined by a device isolation layer, the active region having a first conductivity type;

a first impurity region in the active region;

an anti-fuse gate electrode on the semiconductor substrate, the anti-fuse gate electrode extending across the first impurity region;

an anti-fuse gate dielectric layer between the anti-fuse gate electrode and the first impurity region;

a selection gate electrode on the semiconductor substrate, the selection gate electrode extending across the active region, the selection gate electrode being spaced apart from the anti-fuse gate electrode;

a selection gate dielectric layer between the selection gate electrode and the active region;

a second impurity region in the active region between the selection gate electrode and the anti-fuse gate electrode, the second impurity region being connected to the first impurity region, the first impurity region not under the selection gate electrode; and

a dummy impurity region in the active region on a side of the anti-fuse gate electrode, the dummy impurity region being spaced apart from the second impurity region,

the first and second impurity regions having impurities of a second conductivity type, the first impurity region having an impurity concentration less than an impurity concentration of the second impurity region,

wherein the first impurity region is shallower than the second impurity region from a top surface of the semiconductor substrate,

wherein the anti-fuse gate electrode is provided in plural, and

a portion of the device isolation layer is between adjacent anti-fuse gate electrodes,

wherein the dummy impurity region includes impurities of the second conductivity type and has substantially a same impurity concentration as the second impurity region.

2. The device of claim 1 , wherein the dummy impurity region is in contact with the device isolation layer.

3. The device of claim 1 , wherein a distance between the device isolation layer and a sidewall of the anti-fuse gate electrode is less than a distance between the anti-fuse gate electrode and the selection gate electrode.

4. The device of claim 1 , wherein a bottom surface of the first impurity region is higher than a bottom surface of the second impurity region.

5. The device of claim 1 , wherein the selection gate electrode has a width that is substantially the same as the anti-fuse gate electrode.

6. The device of claim 1 , further comprising:

a third impurity region in the active region of a side of the selection gate electrode, the third impurity region being spaced apart from the second impurity region,

wherein the third impurity region includes impurities of the second conductivity type and has substantially the same impurity concentration as the second impurity region.

7. A semiconductor memory device, comprising:

a semiconductor substrate including an active region defined by a device isolation layer, the active region having a first conductivity type;

a plurality of pairs of anti-fuse gate electrodes extending along a first direction and crossing the active region;

a plurality of pairs of selection gate electrodes between the pairs of anti-fuse gate electrodes and crossing the active region, the pairs of selection gate electrodes extending along the first direction;

first impurity regions including impurities of a second conductivity type that are doped in the active region below the pairs of the anti-fuse gate electrodes and not the pairs of the selection gate electrodes;

anti-fuse gate dielectric layers between the anti-fuse gate electrodes and the first impurity regions;

selection gate dielectric layers between the selection gate electrodes and the active region; and

second impurity regions between the selection gate electrodes and the anti-fuse gate electrodes and doped with impurities of the second conductivity type;

third impurity regions between adjacent selection gate electrodes and doped with impurities of the second conductivity type;

a bit line connected to the third impurity regions and crossing the pairs of the anti-fuse gate electrodes and the pairs of the selection gate electrodes to extend along a second direction perpendicular to the first direction; and

a dummy impurity region in the active region between a pair of the anti-fuse gate electrodes, the dummy impurity being doped with impurities of the second impurity region;

wherein the dummy impurity region and the second impurity region have substantially the same impurity concentration of the second conductivity type,

wherein an impurity concentration of the second conductivity type is less in the first impurity region than in the second impurity regions.

8. The device of claim 7 , wherein the device isolation layer has a portion thereof that extends between adjacent anti-fuse gate electrodes, the device isolation layer defining a plurality of active regions.

9. The device of claim 8 , wherein a distance between the portion of the device isolation layer and a sidewall of the anti-fuse gate electrode is less than a distance between the anti-fuse gate electrode and the selection gate electrode.

10. The device of claim 7 , wherein

the anti-fuse gate electrodes that are adjacent to each other are spaced apart from each other by a first distance, and

the anti-fuse gate electrode and an adjacent selection gate electrode are spaced apart from each other by a second distance that is substantially the same as the first distance.

11. The device of claim 7 , wherein the anti-fuse gate electrode has a width that is less than a width of the first impurity region.

12. The device of claim 7 , wherein the first impurity region has a depth that is less than a depth of the second impurity region.

13. The device of claim 7 , wherein the third impurity region is spaced apart from the second impurity region, and

wherein the second impurity region and the third impurity region have substantially the same impurity concentration of the second conductivity type.