Semiconductor device package and method of manufacturing the same

1. A semiconductor device package, comprising:

a substrate including a conductive layer;

a first semiconductor device disposed on the substrate, the first semiconductor device including a first lateral surface substantially perpendicular to the substrate;

a first underfill disposed between the substrate and the first semiconductor device, the first underfill including a first lateral surface substantially coplanar to the first lateral surface of the first semiconductor device;

a second semiconductor device disposed on the substrate, the second semiconductor device including a first lateral surface substantially perpendicular to the substrate;

a second underfill disposed between the substrate and the second semiconductor device, the second underfill including a first lateral surface substantially coplanar to the first lateral surface of the second semiconductor device;

a first encapsulant encapsulating the first semiconductor device, the second semiconductor device, the first underfill and the second underfill;

a third semiconductor device disposed on the first encapsulant, the third semiconductor device including a first lateral surface substantially perpendicular to the first encapsulant;

a third underfill disposed between the first encapsulant and the third semiconductor device, the third underfill including a first lateral surface substantially coplanar to the first lateral surface of the third semiconductor device;

a fourth semiconductor device disposed on the first encapsulant, the fourth semiconductor device including a first lateral surface substantially perpendicular to the first encapsulant; and

a fourth underfill disposed between the first encapsulant and the fourth semiconductor device, the fourth underfill including a first lateral surface substantially coplanar to the first lateral surface of the fourth semiconductor device,

wherein at least one interconnection element is disposed in the first encapsulant and electrically connected to the substrate.

2. The semiconductor device package of claim 1 , wherein the first semiconductor device and the second semiconductor device are electrically connected through the conductive layer of the substrate.

3. The semiconductor device package of claim 1 , wherein

a second lateral surface of the first underfill opposite to the first lateral surface partially covers a second lateral surface of the first semiconductor device opposite to the first lateral surface or a second lateral surface opposite to the first lateral surface of the second underfill partially covers a second lateral surface opposite to the first lateral surface of the second semiconductor device.

4. The semiconductor device package of claim 1 , wherein

the first semiconductor device includes a second lateral surface opposite to the first lateral surface of the first semiconductor device,

the first underfill includes a second lateral surface opposite to the first lateral surface of the first underfill, and

the second lateral surface of the first underfill is slanted with respect to the second lateral surface of the first semiconductor device.

5. The semiconductor device package of claim 1 , wherein

the second semiconductor device includes a second lateral surface opposite to the first lateral surface of the second semiconductor device,

the second underfill includes a second lateral surface opposite to the first lateral surface of the second underfill, and

the second lateral surface of the second underfill is slanted with respect to the second lateral surface of the second semiconductor device.

6. The semiconductor device package of claim 1 , wherein the first and second semiconductor devices are flip-chip type semiconductor devices.

7. The semiconductor device package of claim 1 , wherein

a second lateral surface of the third underfill opposite to the first lateral surface partially covers a second lateral surface of the third semiconductor device opposite to the first lateral surface or a second lateral surface opposite to the first lateral surface of the fourth underfill partially covers a second lateral surface opposite to the first lateral surface of the fourth semiconductor device.

8. The semiconductor device package of claim 1 , wherein

the third semiconductor device includes a second lateral surface opposite to the first lateral surface of the third semiconductor device,

the third underfill includes a second lateral surface opposite to the first lateral surface of the third underfill, and

the second lateral surface of the third underfill is slanted with respect to the second lateral surface of the third semiconductor device.

9. The semiconductor device package of claim 1 , wherein

the fourth semiconductor device includes a second lateral surface opposite to the first lateral surface of the fourth semiconductor device,

the fourth underfill includes a second lateral surface opposite to the first lateral surface of the fourth underfill, and

the second lateral surface of the fourth underfill is slanted with respect to the second lateral surface of the fourth semiconductor device.

10. The semiconductor device package of claim 1 , wherein the third and fourth semiconductor devices are flip-chip type semiconductor devices.

11. The semiconductor device package of claim 1 , wherein the third and fourth semiconductor devices are electrically connected through the at least one interconnection element.

12. The semiconductor device package of claim 11 , wherein the third and fourth semiconductor devices are electrically connected through the conductive layer of the substrate.

13. The semiconductor device package of claim 11 , wherein the first, second, third and fourth semiconductor devices are electrically connected through the conductive layer of the substrate.

14. The semiconductor device package of claim 1 , further comprising a second encapsulant encapsulating the third and fourth semiconductor devices and the third and fourth underfills.

15. The semiconductor device package of claim 14 , wherein a backside of the third semiconductor device or a backside of the fourth semiconductor device is exposed from the second encapsulant.

16. The semiconductor device package of claim 1 , wherein

the first underfill includes a second lateral surface opposite to the first lateral surface of the first underfill, and

the first and second lateral surfaces of the first underfill are non-parallel to each other.

17. The semiconductor device package of claim 1 , wherein

the third underfill includes a second lateral surface opposite to the first lateral surface of the first underfill, and

the first and second lateral surfaces of the third underfill are non-parallel to each other.