Method of forming air-gap spacers and gate contact over active region and the resulting device
A device including a substrate and at least one fin formed over the substrate. At least one transistor is integrated with the fin at a top portion of the fin. The transistor includes an active region comprising a source, a drain and a channel region between the source and drain. A gate structure is formed over the channel region, and the gate structure includes a HKMG and air-gap spacers formed on opposite sidewalls of the HKMG. Each of the air-gap spacers includes an air gap that is formed along a trench silicide region, and the air-gap is formed below a top of the HKMG. A gate contact is formed over the active region.
1. A device comprising: a substrate; at least one fin formed over the substrate; at least one transistor integrated with the fin at a top portion of the fin, the transistor comprising: an active region comprising a source, a drain and a channel region between the source and drain; a gate structure over the channel region, the gate structure comprising a high dielectric constant metal gate (HKMG) and first air-gap spacers formed on opposite sidewalls of the HKMG, wherein each of the first air-gap spacers comprises an air gap that is formed along a first trench silicide (TS) region, and the aft-gap is formed below a top of the HKMG, wherein the first TS region comprises first TS metallization formed over the source and drain; a gate contact formed over the active region; and a source/drain contact formed over a second TS region comprising second TS metallization in a second region of the substrate, wherein the source/drain contact directly contacts second aft gap spacers formed along the second TS region, wherein the gate contact and source/drain contact are self-aligned.
2. The device according to claim 1 , further comprising a TS cap formed over the first TS metallization.
3. The device according to claim 1 , wherein the TS cap comprises silicon carbide (SiC).
4. The device according to claim 1 , wherein the source and drain are epitaxial source and drain.
5. A method comprising:
forming at least one fin on a semiconductor substrate;
forming at least one active region having a source, a drain, and a channel region between the source and drain;
forming at least one gate structure over the channel region, the gate structure comprising a high dielectric constant metal gate (HKMG) and first air-gap spacers formed on opposite sidewalls of the HKMG,
wherein each of the first air-gap spacers comprises an air gap that is formed along a first trench silicide (TS) region, and the air-gap is formed below a top of the gate electrode, wherein the first TS region comprises first TS metallization formed over the source and drain;
forming a gate contact over the gate electrode; and
forming a source/drain contact formed over a second TS region comprising second TS metallization in a second region of the substrate, wherein the source/drain contact directly contacts second air gap spacers formed along the second TS region,
wherein the gate contact and source/drain contact are self-aligned.
6. The method according to claim 5 , further comprising: forming a TS cap over the first TS metallization.
7. The method according to claim 6 , wherein the TS cap comprises silicon carbide (SiC).
8. The method according to claim 6 , further comprising:
forming self-aligned gate contact over the gate electrode.
9. The method according to claim 5 , wherein the source and drain are epitaxial source and drain.
10. The method according to claim 8 , wherein the first air-gap spacers comprise a material selected from a silicon oxide based material or silicon nitride based material.
11. A device comprising:
a substrate;
a first fin and second fin formed over the substrate;
a first transistor integrated with the first fin at a top portion of the first fin in a first region of the substrate, and a second transistor integrated with the second fin at a top portion of the second fin in a second region of the substrate, the first transistor comprising:
an active region comprising a source, a drain and a channel region between the source and drain;
a gate structure over the channel region, the gate structure comprising a high dielectric constant metal gate (HKMG) and first air-gap spacers formed on opposite sidewalls of the HKMG,
wherein each of the first air-gap spacers comprises an air gap that is formed along a first trench silicide (TS) region, and the air-gap is formed below a top of the HKMG;
a self-aligned gate contact formed over the active region of the first transistor; and
a self-aligned source/drain contact formed over a second TS region comprising second TS metallization in a second region of the substrate, wherein the source/drain contact directly contacts second air gap spacers formed along the second TS region.
12. The device according to claim 11 , wherein the first TS region comprises TS metallization formed over the source and drain of the first transistor.
13. The device according to claim 12 , further comprising a TS cap formed over the first TS metallization.
14. The device according to claim 13 , wherein the TS cap comprises silicon carbide (SiC).
15. The device according to claim 11 , wherein:
the first source and drain of the first transistor are epitaxial source and drain, and
the first air-gap spacers comprise a material selected from a silicon oxide based material or silicon nitride based material.
16. The device according to claim 1 , further comprising a second TS cap formed over the first TS metallization.
17. The device according to claim 5 , further comprising a second TS cap formed over the first TS metallization.
18. The device according to claim 11 , wherein the second air-gap spacers comprise a material selected from a silicon oxide based material or silicon nitride based material.