Non-planar I/O and logic semiconductor devices having different workfunction on common substrate
Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.
1. An integrated circuit structure, comprising:
a first N-type fin-FET device having a first fin, the first fin having a first sidewall at a first end of the fin and a second sidewall at a second end of the fin, the first sidewall opposite the second sidewall, and the first N-type fin-FET device comprising a first gate electrode over the first end of the first fin and adjacent to the first sidewall of the first fin, a second gate electrode over the second end of the first fin and adjacent to the second sidewall of the first fin, and a third gate electrode over the first fin and between the first and second gate electrodes, wherein the first, second and third gate electrodes have a first workfunction; and
a second N-type fin-FET device having a second fin, the second N-type fin-FET device comprising a fourth gate electrode over the second fin, wherein the fourth gate electrode has a second workfunction different than the first workfunction.
2. The integrated circuit structure of claim 1 , wherein the first N-type fin-FET device is a logic transistor, and the second N-type fin-FET device is an I/O transistor.
3. The integrated circuit structure of claim 1 , further comprising:
a first gate dielectric between the first fin and the first gate electrode;
a second gate dielectric between the first fin and the second gate electrode;
a third gate dielectric between the first fin and the third gate electrode; and
a fourth gate dielectric between the second fin and the fourth gate electrode.
4. The integrated circuit structure of claim 3 , wherein the first, second, third and fourth gate dielectrics comprise hafnium and oxygen.
5. An integrated circuit structure, comprising:
a first P-type fin-FET device having a first fin, the first fin having a first sidewall at a first end of the fin and a second sidewall at a second end of the fin, the first sidewall opposite the second sidewall, and the first P-type fin-FET device comprising a first gate electrode over the first end of the first fin and adjacent to the first sidewall of the first fin, a second gate electrode over the second end of the first fin and adjacent to the second sidewall of the first fin, and a third gate electrode over the first fin and between the first and second gate electrodes, wherein the first, second and third gate electrodes have a first workfunction; and
a second P-type fin-FET device having a second fin, the second P-type fin-FET device comprising a fourth gate electrode over the second fin, wherein the fourth gate electrode has a second workfunction different than the first workfunction.
6. The integrated circuit structure of claim 5 , wherein the first P-type fin-FET device is a logic transistor, and the second P-type fin-FET device is an I/O transistor.
7. The integrated circuit structure of claim 6 , further comprising:
a first gate dielectric between the first fin and the first gate electrode;
a second gate dielectric between the first fin and the second gate electrode;
a third gate dielectric between the first fin and the third gate electrode; and
a fourth gate dielectric between the second fin and the fourth gate electrode.
8. The integrated circuit structure of claim 7 , wherein the first, second, third and fourth gate dielectrics comprise hafnium and oxygen.
9. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first N-type fin-FET device having a first fin, the first fin having a first sidewall at a first end of the fin and a second sidewall at a second end of the fin, the first sidewall opposite the second sidewall, and the first N-type fin-FET device comprising a first gate electrode over the first end of the first fin and adjacent to the first sidewall of the first fin, a second gate electrode over the second end of the first fin and adjacent to the second sidewall of the first fin, and a third gate electrode over the first fin and between the first and second gate electrodes, wherein the first, second and third gate electrodes have a first workfunction; and
a second N-type fin-FET device having a second fin, the second N-type fin-FET device comprising a fourth gate electrode over the second fin, wherein the fourth gate electrode has a second workfunction different than the first workfunction.
10. The computing device of claim 9 , further comprising:
a memory coupled to the board.
11. The computing device of claim 9 , further comprising:
a communication chip coupled to the board.
12. The computing device of claim 9 , further comprising:
a camera coupled to the board.
13. The computing device of claim 9 , further comprising:
a battery coupled to the board.
14. The computing device of claim 9 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
15. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first P-type fin-FET device having a first fin, the first fin having a first sidewall at a first end of the fin and a second sidewall at a second end of the fin, the first sidewall opposite the second sidewall, and the first P-type fin-FET device comprising a first gate electrode over the first end of the first fin and adjacent to the first sidewall of the first fin, a second gate electrode over the second end of the first fin and adjacent to the second sidewall of the first fin, and a third gate electrode over the first fin and between the first and second gate electrodes, wherein the first, second and third gate electrodes have a first workfunction; and
a second P-type fin-FET device having a second fin, the second P-type fin-FET device comprising a fourth gate electrode over the second fin, wherein the fourth gate electrode has a second workfunction different than the first workfunction.
16. The computing device of claim 15 , further comprising:
a memory coupled to the board.
17. The computing device of claim 15 , further comprising:
a communication chip coupled to the board.
18. The computing device of claim 15 , further comprising:
a camera coupled to the board.
19. The computing device of claim 15 , further comprising:
a battery coupled to the board.
20. The computing device of claim 15 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.