IP Library › Granted Patent US 10,897,131

Granted Patent B2

US 10,897,131 · App. 15/878,421 · Granted Jan 19, 2021

Electrostatic discharge protection circuit for bypassing an ESD current

Inventors: Yu-Cheng Liao (Yunlin County, TW); Ting-Yao Lin (Taichung, TW); Ping-Chen Chang (Pingtung County, TW); Tien-Hao Tang (Hsinchu, TW)

Assignee: UNITED MICROELECTRONICS CORP.

H02H9/046 H01L27/0266 H01L27/0285 H01L27/0288 H02H1/0007 H01L27/0629

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Quick Facts

Patent No.: US 10,897,131
App. No.: 15/878,421
Granted: Jan 19, 2021
Kind: B2

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USPTO Patent Center↗ Full Patent PDF↗

Abstract

An electrostatic discharge (ESD) protection circuit has a first power node, a second power node, an ESD detect circuit, an ESD device and a voltage controlled switch. The ESD detect circuit is coupled between the first power node and the second power node for detecting an ESD current to output a control signal at a output terminal of the ESD detect circuit. The ESD device is coupled between the first power node and the second power node for leaking the ESD current. The voltage controlled switch is used to couple a body of the ESD device to the second power node according to at least a voltage level of the control signal.

Claims (45)

1. An electrostatic discharge (ESD) protection circuit, comprising:

a first power node;

a second power node;

an ESD detect circuit, coupled between the first power node and the second power node, and configured to detect an ESD current to output a first control signal at a first output terminal of the ESD detect circuit and output a second control signal at a second output terminal of the ESD detect circuit;

an ESD device, coupled between the first power node and the second power node, and configured to couple the first power node to the second power node to leak the ESD current according to a voltage level of the second control signal; and

a voltage controlled switch, configured to couple a body of the ESD device to the second power node according to at least a voltage level of the first control signal.

2. The ESD protection circuit of claim 1 , wherein the voltage controlled switch couples the body of the ESD device to the second power node according to the voltage level of the first control signal and the voltage level of the second control signal.

3. The ESD protection circuit of claim 1 , wherein the voltage level of the first control signal is complementary to the voltage level of the second control signal.

4. The ESD protection circuit of claim 1 , wherein the ESD detect circuit comprises:

a resistor-capacitor (RC) circuit, coupled to the first power node and the second power node, and comprising a resistor and a capacitor, a second end of the resistor and a first end of the capacitor being coupled to the first output terminal; and

an inverter, an input terminal of the inverter being coupled to the first output terminal, and an output terminal of the inverter being coupled to a control end of the ESD device.

5. The ESD protection circuit of claim 4 , wherein a first end of the resistor is coupled to the first power node, and a second end of the capacitor is coupled to the second power node.

6. The ESD protection circuit of claim 4 , wherein the ESD device couples the first power node to the second power node to leak the ESD current according to a voltage level of the output terminal of the inverter.

7. The ESD protection circuit of claim 4 , wherein the inverter comprises:

a first transistor, a control end of the first transistor being coupled to the first output terminal, a first end of the first transistor being coupled to the first power node, and a second end of the first transistor being coupled to the control end of the ESD device; and

a second transistor, a control end of the second transistor being coupled to the first output terminal, a first end of the second transistor being coupled to the control end of the ESD device, and a second end of the second transistor being coupled to the second power node.

8. The ESD protection circuit of claim 1 , wherein the voltage controlled switch comprises a third transistor, a first end of the third transistor is coupled to the body of the ESD device, a second end of the third transistor is coupled to the second power node, and a control end of the third transistor is coupled to the first output terminal.

9. The ESD protection circuit of claim 1 , wherein the voltage controlled switch comprises:

a third transistor, a first end of the third transistor being coupled to the body of the ESD device, a second end of the third transistor being coupled to the second power node, and a control end of the third transistor being coupled to the first output terminal; and

a fourth transistor, a first end of the fourth transistor being coupled to the body of the ESD device, a second end of the fourth transistor being coupled to the second power node, and a control end of the fourth transistor being coupled to the second output terminal.

10. An electrostatic discharge (ESD) protection circuit, comprising:

a first power node;

a second power node;

an ESD detect circuit, comprising:

an inverter, an input terminal of the inverter being coupled to the first output terminal, and an output terminal of the inverter being coupled to a second output terminal of the ESD detect circuit;

an ESD clamp circuit, a first end of the ESD clamp circuit being coupled to the first power node, a second end of the ESD clamp circuit being coupled to the second power node, and a control end of the ESD clamp circuit being coupled to the second output terminal of the ESD detect circuit; and

11. An electrostatic discharge (ESD) protection circuit, comprising:

a first power node;

a second power node;

an ESD detect circuit, a first terminal of the ESD detect circuit being coupled to the first power node, and a second terminal of the ESD detect circuit being coupled to the second power node;

an ESD clamp circuit, a first end of the ESD clamp circuit being coupled to the first power node, a second end of the ESD clamp circuit being coupled to the second power node, a control end of the ESD clamp circuit being coupled to a second output terminal of the ESD detect circuit, and the ESD detect circuit being configured to detect an ESD current to output a first control signal at the first output terminal of the ESD detect circuit; and

a voltage controlled switch, a first end of the voltage controlled switch being coupled to a body of the ESD clamp circuit, a second end of the voltage controlled switch being coupled to the second power node, a first control end of the voltage controlled switch being coupled to a first output terminal of the ESD detect circuit, and the voltage controlled switch being configured to couple the body of the ESD clamp circuit to the second power node according to at least a voltage level of the first control signal;

wherein the ESD detect circuit further outputs a second control signal at the second output terminal of the ESD detect circuit by detecting the ESD current, and the ESD clamp circuit couples the first power node to the second power node to leak the ESD current according to a voltage level of the second control signal.

12. The ESD protection circuit of claim 11 , wherein a second control end of the voltage controlled switch is coupled to the second output terminal of the ESD detect circuit, and the voltage controlled switch couples the body of the ESD clamp circuit to the second power node according to the voltage level of the first control signal and the voltage level of the second control signal.

13. The ESD protection circuit of claim 10 , wherein a first end of the resistor is coupled to the first power node, and a second end of the capacitor is coupled to the second power node.

14. The ESD protection circuit of claim 10 , wherein the ESD clamp circuit couples the first power node to the second power node to leak the ESD current according to a voltage level of the output terminal of the inverter.

15. The ESD protection circuit of claim 10 , wherein the inverter comprises:

a second transistor, a control end of the second transistor being coupled to the first output terminal, a first end of the second transistor being coupled to the control end of the ESD clamp circuit, and a second end of the second transistor being coupled to the second power node.

16. The ESD protection circuit of claim 10 , wherein the voltage controlled switch comprises a third transistor, a first end of the third transistor is coupled to the body of the ESD clamp circuit, a second end of the third transistor is coupled to the second power node, and a control end of the third transistor is coupled to the first output terminal.

17. The ESD protection circuit of claim 10 , wherein the voltage controlled switch comprises:

a third transistor, a first end of the third transistor being coupled to the body of the ESD clamp circuit, a second end of the third transistor being coupled to the second power node, and a control end of the third transistor being coupled to the first output terminal; and

a fourth transistor, a first end of the fourth transistor being coupled to the body of the ESD clamp circuit, a second end of the fourth transistor being coupled to the second power node, and a control end of the fourth transistor being coupled to the second output terminal.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 24, 2018

From: LIAO, YU-CHENG; LIN, TING-YAO; CHANG, PING-CHEN; TANG, TIEN-HAO

To: UNITED MICROELECTRONICS CORP.

Reel/Frame 044707/0017 →

Continuity (1)

Related Publication 20190229531A1 · Jul 25, 2019

Cited By (1)

US 12,731,986