Integrated assemblies having anchoring structures proximate stacked memory cells, and methods of forming integrated assemblies
Some embodiments include an assembly having channel material structures extending upwardly from a conductive structure. Anchor structures are laterally offset from the channel material structures and penetrate into the conductive structure to a depth sufficient to provide mechanical stability to at least a portion of the assembly. The conductive structure may include a first conductive material over a second conductive material, and may be a source line of a three-dimensional NAND configuration. Some embodiments include methods of forming assemblies to have channel material structures and anchor structures.
1. An assembly, comprising:
an insulative material;
a conductive structure over the insulative material;
the conductive structure comprising a first conductive material over a second conductive material;
the conductive structure having an undulating bottom surface along a cross-section;
the undulating bottom surface including a ridge region between a pair of foot regions, with the ridge region being above the foot regions by at least about 30 nm;
the first conductive material having a first primary thickness over the ridge region, and the second conductive material having a second primary thickness over the ridge region;
a stack of materials over the conductive structure, the stack of materials comprising dielectric levels alternating with conductive levels;
channel material structures over the ridge region and extending through the stack of materials into the first conductive material to a first depth which is less than the first primary thickness; and
anchor structures over the foot regions and extending through the stack of materials into the first and second conductive materials to a second depth which is greater than the first primary thickness;
the first and second conductive materials wrapping around bottom regions of the anchor structures;
wherein the ridge region has a lateral dimension of at least about 300 nm between the foot regions;
wherein each individual foot region has a lateral dimension along the cross-section within a range of from about 50 nm to about 500 nm.
2. The assembly of claim 1 wherein the second depth is less than the combined first and second primary thicknesses.
3. The assembly of claim 1 wherein the second depth is greater than the combined first and second primary thicknesses.
4. The assembly of claim 1 wherein the ridge region is above the foot regions by at least about 50 nm.
5. The assembly of claim 1 wherein the ridge region is above the foot regions by a distance within a range of from about 50 nm to about 500 nm.
6. The assembly of claim 1 wherein the lateral dimension is within a range of from about 500 nm to about 5000 nm.
7. The assembly of claim 1 wherein the lateral dimension is within a range of from about 600 nm to about 2500 nm.
8. The assembly of claim 1 further comprising CMOS circuitry coupled with the conductive structure.
9. The assembly of claim 1 wherein the conductive structure, anchor structures and channel material structures are part of a memory tier; and further comprising a CMOS tier under the memory tier and having CMOS circuitry coupled with the conductive structure.