Conversion apparatus, imaging apparatus, electronic apparatus, and conversion method
The present technology relates to a conversion apparatus, an imaging apparatus, an electronic apparatus, and a conversion method that are capable of reducing the scale of a circuit. The conversion apparatus includes: a comparison unit that compares an input voltage of an input signal and a ramp voltage of a ramp signal that varies with time; and a storage unit that holds a code value when a comparison result from the comparison unit is inverted, the holding of the code value by the storage unit being repeated a plurality of times, to generate a digital signal having a predetermined bit number. The predetermined bit number is divided into high-order bits and low-order bits, the low-order bits are acquired earlier than the high-order bits, and the acquired low-order bits and the high-order bits are combined with each other, to generate the digital signal having the predetermined bit number. The present technology can be applied to a portion of an image sensor, in which AD conversion is performed.
1. An imaging apparatus, comprising:
an upper substrate including:
a plurality of pixel blocks; and
a plurality of comparators, wherein each comparator in the plurality of comparators is configured to compare an analog signal conveyed from a corresponding one of the pixel blocks and a reference signal conveyed from a digital to analog converter (DAC);
a lower substrate connected to the upper substrate by Cu-Cu bonding including:
a plurality of latch circuits arranged in a matrix,
wherein each of the latch circuits is configured to receive an output signal of a corresponding one of the comparators and to output a digital signal.
2. The imaging apparatus according to claim 1 , wherein the reference signal is a ramp signal that varies with time.
3. The imaging apparatus according to claim 1 , wherein each of the latch circuits is configured to hold a code value when the output signal of the corresponding comparator is inverted.
4. The imaging apparatus according to claim 1 , wherein the digital signal has a predetermined bit number.
5. The imaging apparatus according to claim 4 , wherein the predetermined bit number is divided into high-order bits and low-order bits.
6. The imaging apparatus according to claim 5 , wherein the low-order bits are acquired earlier than the high-order bits, and the acquired low-order bits and the high-order bits are combined with each other.
7. The imaging apparatus according to claim 5 , wherein the low-order bits are Gray codes.
8. The imaging apparatus according to claim 5 , wherein at least one bit of the low-order bits and the high-order bits is shared.
9. The imaging apparatus according to claim 8 wherein the digital signal is corrected by a value of a bit that is one-order lower than the shared bit.
10. The imaging apparatus according to claim 5 , wherein the reference signal includes a first ramp signal for acquiring the low-order bits and a second ramp signal for acquiring the high-order bits, and wherein the first and second ramp signals have different cycles.
11. An imaging apparatus, comprising:
an upper substrate including:
a plurality of pixel blocks; and
a plurality of first portions of comparators configured to compare an analog signal conveyed from one of the pixel blocks and a reference signal conveyed from a digital to analog converter (DAC);
a lower substrate connected to the upper substrate by Cu-Cu bonding including:
a plurality of second portions of comparators arranged in a matrix; and
a plurality of latch circuits arranged in a matrix;
wherein each of the latch circuits is configured to receive an output signal of a corresponding one of the comparators and output a digital signal.
12. The imaging apparatus according to claim 11 , wherein the reference signal is a ramp signal that varies with time.
13. The imaging apparatus according to claim 11 , wherein each of the latch circuits is configured to hold a code value when the output signal of the corresponding comparator is inverted.
14. The imaging apparatus according to claim 11 , wherein the digital signal has a predetermined bit number.
15. The imaging apparatus according to claim 14 , wherein the predetermined bit number is divided into high-order bits and low-order bits.
16. The imaging apparatus according to claim 15 , wherein the low-order bits are acquired earlier than the high-order bits, and the acquired low-order bits and the high-order bits are combined with each other.
17. The imaging apparatus according to claim 15 , wherein the low-order bits are Gray codes.
18. The imaging apparatus according to claim 15 , wherein at least one bit of the low-order bits and the high-order bits is shared.
19. The imaging apparatus according to claim 18 , wherein the digital signal is corrected by a value of a bit that is one-order lower than the shared bit.
20. The imaging apparatus according to claim 15 , wherein the reference signal includes a first ramp signal for acquiring the low-order bits and a second ramp signal for acquiring the high-order bits, and wherein the first and second ramp signals have different cycles.