IP Library › Granted Patent US 10,923,394
Granted Patent B2
US 10,923,394 · App. 16/357,724 · Granted Feb 16, 2021

Platform and method of operating for integrated end-to-end fully self-aligned interconnect process

Inventors: Robert Clark (Fremont, CA); Kandabara Tapily (Albany, NY); Kai-Hung Yu (Albany, NY)
Assignee: Tokyo Electron Limited
H01L21/76879G05B13/027G05B19/41875H01L21/0228H01L21/02271H01L21/28562H01L21/31116H01L21/67023H01L21/67063H01L21/67161H01L21/67167H01L21/67184H01L21/67196H01L21/67225H01L21/67253H01L21/67276H01L21/67288H01L21/67703H01L21/67742H01L21/67745H01L21/7685H01L21/76802H01L21/76831H01L21/76832H01L21/76834H01L21/76897H01L22/12C23C14/24C23C14/34G05B2219/32368G05B2219/45031H01J37/32H01L21/67017H01L21/67207
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Quick Facts
Patent No.
US 10,923,394
App. No.
16/357,724
Granted
Feb 16, 2021
Kind
B2
Abstract

A method for forming a fully self-aligned via is provided. A workpiece having a pattern of features in a dielectric layer is received into a common manufacturing platform. Metal caps are deposited on the metal features, and a barrier layer is deposited on the metal caps. A first dielectric layer is added to exposed dielectric material. The barrier layer is removed and an etch stop layer is added on the exposed surfaces of the first dielectric layer and the metal caps. Additional dielectric material is added on top of the etch stop layer, then both the additional dielectric material and a portion of the etch stop layer are etched to form a feature to be filled with metal material. An integrated sequence of processing steps is executed within one or more common manufacturing platforms to provide controlled environments. Transfer modules transfer the workpiece between processing modules within and between controlled environments.

Claims (21)

1. A method of preparing for a self-aligned via on a semiconductor workpiece comprising:

using an integrated sequence of processing steps executed on a common manufacturing platform hosting a plurality of processing modules including one or more film-forming modules, one or more etching modules, and one or more transfer modules, the integrated sequence of processing steps comprising:

receiving the workpiece into the common manufacturing platform, the workpiece having a pattern of metal features in a dielectric layer wherein exposed surfaces of the metal features and exposed surfaces of the dielectric layer together define an upper planar surface;

selectively depositing metal caps on the exposed surfaces of the metal features relative to the exposed dielectric material using one of the one or more of the film-forming modules;

selectively forming a recessed pattern of dielectric material around the metal features relative to the dielectric material, with the metal caps forming a bottom surface of the recessed pattern, the metal caps being exposed from a top of the recessed pattern; and

inspecting the workpiece at one or more points of the integrated sequence to detect a non-conformity on the workpiece related to the metal cap deposition and/or recessed pattern formation,

wherein the integrated sequence of processing steps is executed in a controlled environment within the common manufacturing platform and without leaving the controlled environment, and wherein the one or more transfer modules are used to transfer the workpiece between the plurality of processing modules while maintaining the workpiece within the controlled environment.

2. The method of claim 1 , wherein selectively forming the recessed pattern comprises:

depositing a self-assembled monolayer on the metal caps using one of the one or more film-forming modules;

selectively depositing a first dielectric material on the exposed surfaces of the dielectric layer using one of the one or more film-forming modules to form a recess in the first dielectric material; and

etching the workpiece to remove the self-assembled monolayer using one of the one or more etching modules to expose the metal caps at bottom surfaces of the recessed pattern.

3. The method of claim 2 , further comprising:

depositing an etch stop layer over the recessed pattern using one of the one or more film-forming modules; and

depositing a second dielectric material on the etch stop layer to form an interlayer dielectric over the recessed pattern using one of the one or more film-forming modules.

4. The method of claim 2 , wherein inspecting the workpiece at one or more points of the integrated sequence to detect a non-conformity on the workpiece comprises obtaining measurement data related to the metal caps and/or of the exposed surfaces of the dielectric layer to verify that the metal caps are covered by the self-assembled monolayer above a pre-determined monolayer coverage threshold and/or metal nuclei on the exposed surfaces of the dielectric layer is above a predetermined metal nuclei threshold.

5. The method of claim 4 , further comprising implementing a remedial action to ameliorate the non-conformity when the measurement data indicates the non-conformity is present on the workpiece, the remedial action comprises removing the self-assembled monolayer when the pre-determined monolayer coverage threshold is exceeded and/or removing metal nuclei from the dielectric layer when the predetermined metal nuclei threshold is exceeded.

6. The method of claim 2 , wherein inspecting the workpiece at one or more points of the integrated sequence to detect a non-conformity on the workpiece comprises:

obtaining measurement data related to attributes of the metal caps to verify that the self-assembled monolayer is removed from the metal caps; or

obtaining measurement data related to attributes of the first dielectric material to verify that the first dielectric material completely covers the exposed surfaces of the dielectric layer and/or to verify an absence of the first dielectric layer on the exposed surfaces of the metal caps.

7. The method of claim 6 , further comprising implementing a remedial action to ameliorate the non-conformity when the measurement data indicates the non-conformity is present on the workpiece, the remedial action comprises removing self-assembled monolayer from the metals caps based, at least in part, the measurement data related to attributes of the metal caps and/or removing the first dielectric layer from the exposed surfaces of the metal caps based, at least in part, on measurement data related to attributes of the first dielectric material.

8. The method of claim 1 , wherein the metal caps comprise ruthenium, cobalt, tungsten, or molybdenum.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2019
From: CLARK, ROBERT; TAPILY, KANDABARA; YU, KAI-HUNG
To: TOKYO ELECTRON LIMITED
Reel/Frame 049946/0547 →
Continuity (5)
Provisional Application 62788195 · Jan 4, 2019
Provisional Application 62787607 · Jan 2, 2019
Provisional Application 62787608 · Jan 2, 2019
Provisional Application 62645685 · Mar 20, 2018
Related Publication 20190295891A1 · Sep 26, 2019
Cited By (2)
US 12,622,210 US 12,680,869