Contact plugs and methods forming same
A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.
1. An integrated circuit device comprising:
a first Inter-Layer Dielectric (ILD);
a first gate spacer in the first ILD;
a gate dielectric between opposite portions of the first gate spacer;
a metal gate over the gate dielectric, wherein a top surface of the metal gate, a top end of the first gate spacer, and a top surface of the first ILD are in contact with a bottom surface of a same dielectric layer;
a second ILD over the first ILD;
a source/drain region adjacent to the metal gate;
a source/drain contact plug over and electrically coupling to the source/drain region, wherein the source/drain contact plug penetrates through both the first ILD and the second ILD;
a high-k dielectric contact spacer encircling the source/drain contact plug; and
a source/drain silicide region on top of the source/drain region, wherein the high-k dielectric contact spacer extends lower than a top surface of the source/drain silicide region.
2. The integrated circuit device of claim 1 , wherein the high-k dielectric contact spacer is free from portions directly underlying the source/drain contact plug.
3. The integrated circuit device of claim 2 , wherein the high-k dielectric contact spacer comprises AlxOy or HfO 2 .
4. The integrated circuit device of claim 2 , wherein the high-k dielectric contact spacer comprises SiOCN or SiN.
5. The integrated circuit device of claim 1 , wherein the second ILD is in contact with the first ILD, and the integrated circuit device further comprises a gate contact plug in the second ILD, with a bottom surface of the second ILD substantially coplanar with a bottom surface of the gate contact plug.
6. The integrated circuit device of claim 1 further comprising a high-k dielectric mask between and in contact with both the first ILD and the second ILD, with the source/drain contact plug further penetrating through the high-k dielectric mask.
7. The integrated circuit device of claim 6 , wherein the high-k dielectric mask comprises AlxOy, SiOCN, HfO 2 , or SiN.
8. The integrated circuit device of claim 1 further comprising a second gate spacer between and contacting both the gate dielectric and the first gate spacer, wherein the second gate spacer comprises a low-k dielectric material.
9. The integrated circuit device of claim 8 , wherein the second gate spacer comprises:
a low-k dielectric gate spacer; and
a non-low-k dielectric gate spacer contacting the low-k dielectric gate spacer, wherein one of the low-k dielectric gate spacer and the non-low-k dielectric gate spacer contacts the gate dielectric.
10. The integrated circuit device of claim 9 , wherein the low-k dielectric gate spacer is formed of SiOCN or SiN, with pores formed in the SiOCN or SiN.
11. An integrated circuit device comprising:
a semiconductor region;
a gate stack over the semiconductor region;
a first gate spacer contacting a sidewall of the gate stack, wherein the first gate spacer comprises a low-k dielectric material;
a second gate spacer contacting a sidewall of the first gate spacer, wherein the second gate spacer comprises:
an L-shape layer, and an additional layer overlapping a bottom leg of the L-shaped layer, wherein a first edge of the L-shape layer and a second edge of the additional layer are flushed with each other, and the second edge of the additional layer is higher than a bottom surface of the gate stack;
a source/drain region on a side of the gate stack;
a source/drain silicide region over the source/drain region;
a source/drain contact plug over and joined to the source/drain silicide region;
a high-k dielectric contact spacer encircling the source/drain contact plug, wherein the high-k dielectric contact spacer extends lower than a top surface of the source/drain silicide region;
a contact etch stop layer having a vertical portion contacting the second gate spacer;
an inter-layer dielectric contacting the contact etch stop layer; and
a dielectric layer over the first gate spacer, the second gate spacer, the contact etch stop layer, and the inter-layer dielectric in a vertical direction, wherein the dielectric layer is in physical contact with the first gate spacer, the second gate spacer, the contact etch stop layer, and the inter-layer dielectric.
12. The integrated circuit device of claim 11 , wherein the second gate spacer comprises a first sub-spacer formed of the low-k dielectric material, and a second sub-spacer formed of silicon oxide or a high-k dielectric material.
13. The integrated circuit device of claim 12 , wherein the first sub-spacer is in contact with the gate stack.
14. The integrated circuit device of claim 12 , wherein the second sub-spacer is in contact with the gate stack.
15. An integrated circuit device comprising:
a semiconductor fin;
a gate stack on sidewalls and a top surface of the semiconductor fin;
a gate spacer on a sidewall of the gate stack;
a contact etch stop layer having a vertical portion contacting the gate spacer;
an inter-layer dielectric contacting the contact etch stop layer;
a high-k dielectric hard mask over and contacting the gate spacer, the contact etch stop layer, and the inter-layer dielectric;
a source/drain region on a side of the gate stack;
a source/drain silicide region over the source/drain region;
a source/drain contact plug over and joined to the source/drain silicide region; and
a high-k dielectric contact spacer encircling the source/drain contact plug, wherein the high-k dielectric contact spacer extends lower than a top surface of the source/drain silicide region.
16. The integrated circuit device of claim 15 , wherein the gate spacer comprises:
a first gate spacer contacting a sidewall of the gate stack, wherein the first gate spacer comprises a low-k dielectric material; and
a second gate spacer contacting a sidewall of the first gate spacer.
17. The integrated circuit device of claim 16 , wherein the high-k dielectric hard mask comprises AlxOy or SiOCN.
18. The integrated circuit device of claim 17 , wherein the high-k dielectric hard mask comprises AlxOy.
19. The integrated circuit device of claim 17 , wherein the high-k dielectric hard mask comprises SiOCN.