Contact plugs and methods forming same
A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.
1 . A device comprising:
a substrate;
two conductive features positioned apart from each other over the substrate;
a graded porous dielectric structure positioned between the two conductive features, wherein the graded porous dielectric structure comprises:
a first portion having a first porosity; and
a second portion having a second porosity, wherein the second porosity is higher than the first porosity; and
a dielectric layer positioned between one of the two conductive features and the graded porous dielectric structure, wherein the dielectric layer comprises a gate spacer, and the gate spacer comprises:
an L-shaped layer comprising a horizontal leg and a vertical leg connecting to the horizontal leg, wherein the vertical leg contacts the graded porous dielectric structure; and
an outer spacer overlapping the horizontal leg, wherein the outer spacer contacts the vertical leg to form a vertical interface.
2 . The device of claim 1 , wherein the one of the two conductive features comprises a contact plug.
3 . The device of claim 1 , wherein the two conductive features comprise a gate structure.
4 . The device of claim 3 , wherein the two conductive features further comprise a source/drain region.
5 . The device of claim 4 , wherein the first portion of the graded porous dielectric structure is positioned between the second portion and the gate structure.
6 . The device of claim 4 , wherein the second portion of the graded porous dielectric structure is positioned between the first portion and the gate structure.
7 . The device of claim 1 , wherein the graded porous dielectric structure comprises silicon, carbon, and nitrogen.
8 . The device of claim 1 , wherein the one of the two conductive features comprises a gate structure, and the device further comprises a fin positioned between the gate structure and the substrate.
9 . The device of claim 8 further comprising:
a dielectric hard mask over the gate structure, wherein the dielectric hard mask is formed of a same dielectric material as the graded porous dielectric structure, with the graded porous dielectric structure being more porous than the dielectric hard mask; and
an inter-layer dielectric over the dielectric hard mask.
10 . The device of claim 8 further comprising:
a source/drain region adjacent to the gate structure;
a source/drain contact plug over and electrically coupling to the source/drain region;
a high-k dielectric contact spacer encircling the source/drain contact plug; and
a source/drain silicide region between the source/drain region and the source/drain contact plug, wherein the high-k dielectric contact spacer extends lower than a top surface of the source/drain silicide region.
11 . The device of claim 10 , wherein the high-k dielectric contact spacer has a first edge contacting a second edge of the source/drain silicide region.
12 . A device comprising:
a semiconductor fin;
a gate stack on the semiconductor fin, wherein the gate stack comprises:
a gate electrode;
a gate dielectric comprising a bottom portion overlapped by the gate electrode, and sidewall portions contacting sidewalls of the gate electrode;
a graded porous dielectric spacer on a first sidewall of the gate stack, wherein the graded porous dielectric spacer physically contacts the semiconductor fin, and wherein the graded porous dielectric spacer comprises:
a first layer having a first porosity; and
a second layer on a second sidewall of the first layer, the second layer having a second porosity greater than the first porosity; and
a source/drain region on a side of the gate stack, wherein the graded porous dielectric spacer is laterally between the gate stack and the source/drain region.
13 . The device of claim 12 , wherein both of the first layer and the second layer comprise silicon oxynitride.
14 . The device of claim 13 , wherein both of the first layer and the second layer comprise silicon oxy carbo-nitride.
15 . The device of claim 12 , wherein the second layer that has greater porosity than the first layer is spaced apart from the gate electrode by the first layer.
16 . The device of claim 12 , wherein the sidewall portions of the gate dielectric form vertical interfaces with the gate electrode.
17 . The device of claim 12 , wherein both of the first layer and the second layer of the graded porous dielectric spacer are in physical contact with the semiconductor fin.
18 . A device comprising:
a semiconductor region;
a gate stack on the semiconductor region;
a source/drain region adjacent to the gate stack and extending into the semiconductor region; and
a gate spacer on a sidewall of the gate stack, wherein the gate spacer comprises a first portion and a second portion formed of low-k dielectric materials, and wherein the first portion and the second portion are formed of a same dielectric material, and have different porosity values.
19 . The device of claim 18 , wherein the same dielectric material comprises SiON.
20 . The device of claim 18 , wherein the first portion and the second portion have a vertical interface in between.