Extension region for a semiconductor device
A semiconductor device herein includes doped extension regions for silicon and silicon germanium nanowires. The nanowires can be selectively grown and recessed into a gate spacer. The semiconductor device can include a gate structure including the gate spacer; the nanowire or channel extending through the gate structure such that an end of the channel is recessed within a recess in said gate spacer; an extension region in contact with the end of the channel within the recess, the extension region being formed of an extension material having a different composition than a channel material of the channel such that a strain is provided in the channel; and a source-drain contact in contact with the extension region and adjacent to the gate structure.
1. A semiconductor device comprising:
a gate structure including a gate spacer;
a channel extending through the gate structure such that an end of the channel is recessed within a recess in said gate spacer;
an extension region in contact with the end of the channel within the recess, the extension region being formed of an extension material having a different composition than a channel material of the channel such that a strain is provided in the channel; and
a source-drain contact in contact with the extension region and adjacent to the gate structure, wherein
the extension region is disposed between the channel and the source-drain contact and covers an entirety of the recessed end of the channel.
2. The semiconductor device according to claim 1 , further comprising:
a second channel extending through a second gate structure such that an end of the second channel is recessed within a second recess in said gate spacer;
a second extension region in contact with the end of the second channel within the second recess, the second extension region being formed of a second extension material having a different composition than a second channel material of the second channel such that a strain is provided in the second channel; and
a second source-drain contact in contact with the second extension region and adjacent to the gate structure, wherein
the second extension region is disposed between the second channel and the second source-drain contact and covers an entirety of the recessed end of the second channel.
3. The semiconductor device according to claim 1 , wherein the channel comprises a nanowire, and an end of the nanowire is recessed at a depth less than a thickness of the gate spacer.
4. The semiconductor device according to claim 3 , wherein the gate spacer has a thickness of 30-100 angstroms.
5. The semiconductor device according to claim 3 , wherein the nanowire comprises silicon.
6. The semiconductor device according to claim 3 , wherein the extension region comprises SiGe.
7. The semiconductor device according to claim 3 , wherein the extension region is epitaxially grown from the end of the channel.
8. The semiconductor device according to claim 7 , wherein epitaxial growth of the extension region is stopped when an end of the extension region opposite the end of the nanowire is disposed flush with a sidewall of the gate spacer.
9. The semiconductor device according to claim 7 , wherein epitaxial over-growth of the extension region is recessed such that an end of the extension region opposite the end of the nanowire is disposed flush with a sidewall of the gate spacer.
10. The semiconductor device according to claim 7 , wherein the extension material is doped in-situ during epitaxial growth of the extension material.
11. The semiconductor device according to claim 3 , wherein the extension region is doped with Ge.
12. The semiconductor device according to claim 11 , wherein the extension region comprises doped SiGe including germanium in the range of 20% to 70%.
13. The semiconductor device according to claim 3 , wherein the source-drain contact is doped with dopants and an anneal diffuses the dopants form the source-drain contacts into the extension region.
14. The semiconductor device according to claim 1 , wherein extension region is enriched with Ge.
15. A semiconductor device comprising:
a p-type lateral nanowire coupled to a p-type source-drain region by a first connecting structure through a first opening in a gate spacer;
an n-type lateral nanowire provided in vertical stacked relation to the p-type nanowire and coupled to an n-type source-drain region by a second connecting structure through a second opening in the gate spacer; and
an electrode structure comprising a p-type electrode contacting said p-type source-drain, and an n-type electrode contacting said n-type source-drain, said n-type electrode being electrically insulated from said p-type electrode by a dielectric, and at least one of said first and second connecting structures comprising an extension doping region within a respective opening in the gate spacer.
16. The semiconductor device according to claim 15 , wherein said at least one connecting structure comprises doped SiGe.
17. The semiconductor device according to claim 16 , wherein said doped SiGe comprises germanium in the range of 20% to 70%.
18. The semiconductor device according to claim 15 , wherein the first connecting structure is epitaxially grown from an end of the p-type lateral nanowire, and the second connecting structure is epitaxially grown from an end of the n-type lateral nanowire.
19. The semiconductor device according to claim 16 , wherein epitaxial growth of the first connecting structure and the second connecting structure is stopped when an end of the first connecting structure opposite the end of the p-type lateral nanowire and an end of the second connecting structure opposite the end of the n-type lateral nanowire are disposed flush with a sidewall of the gate spacer.
20. The semiconductor device according to claim 18 , wherein the first connecting structure and the second connecting structure are doped in-situ during epitaxial growth of the first connecting structure and the second connecting structure.