IP Library Granted Patent US 10,937,889
Granted Patent B2
US 10,937,889 · App. 16/662,782 · Granted Mar 2, 2021

Forming thermally stable salicide for salicide first contacts

Inventors: Praneet Adusumilli (Albany, NY); Emre Alptekin (Wappingers Falls, NY); Christian Lavoie (Pleasantville, NY); Ahmet S. Ozcan (San Jose, CA)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
H01L29/665H01L21/28518H01L21/823431H01L29/41791H01L29/66545H01L29/66795H01L29/785H01L21/823425H01L21/823475H01L29/045H01L29/0847H01L2029/7858
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Quick Facts
Patent No.
US 10,937,889
App. No.
16/662,782
Granted
Mar 2, 2021
Kind
B2
Abstract

A method for forming a salicide includes forming, on at least one semiconductor fin, at least one source/drain (S/D) region including a (111) facet and having a cross-sectional quadrilateral shape, forming a conductive material on the (111) facet, annealing the conductive material to form a silicide on the (111) facet, and forming at least one contact to the silicide.

Claims (45)

1. A method for forming a salicide, comprising:

forming, on top surfaces of a plurality of semiconductor fins, a plurality of source/drain (S/D) regions separated in a non-merged configuration each including a (111) facet and having a cross-sectional quadrilateral shape;

forming a conductive material on all facets of the plurality of S/D regions in a wrapped around configuration;

annealing the conductive material to form a silicide on the (111) facets; and

forming at least one contact to the silicide.

2. The method as recited in claim 1 , wherein forming the at least one contact further includes:

forming a dielectric layer over the plurality of S/D regions;

forming at least one contact hole in the dielectric layer; and

forming the at least one contact to the silicide in the at least one contact hole.

3. The method as recited in claim 2 , wherein forming the at least one contact hole further includes forming a plurality of contact holes over a portion of the plurality of S/D regions.

4. The method as recited in claim 3 , wherein forming the at least one contact further includes forming a plurality of contacts to the silicide in the plurality of contact holes over the portion of the plurality of S/D regions to reduce capacitance in a partially strapped configuration.

5. The method as recited in claim 1 , wherein annealing the conductive material further includes performing a thermally stabilizing anneal process with a laser anneal at a temperature of between about 900 to 1100 degrees C. for less than or equal to 1 millisecond.

6. The method as recited in claim 5 , wherein annealing the conductive material further includes performing an additional anneal process to continue to form the silicide.

7. A method for forming a salicide, comprising:

forming, on top surfaces of a plurality of semiconductor fins, a plurality of source/drain (S/D) regions separated in a non-merged configuration each including a (111) facet and having a cross-sectional quadrilateral shape;

forming a conductive material on the (111) facets;

annealing the conductive material to form a silicide on the (111) facets, including forming merged silicides between the plurality of S/D regions; and

forming at least one contact to the silicide.

8. The method as recited in claim 7 , wherein forming the at least one contact further includes:

forming a dielectric layer over the plurality of S/D regions;

forming at least one contact hole in the dielectric layer; and

forming the at least one contact to the silicide in the at least one contact hole.

9. The method as recited in claim 8 , wherein forming the at least one contact hole further includes forming a plurality of contact holes over a portion of the plurality of S/D regions.

10. The method as recited in claim 9 , wherein forming the at least one contact further includes forming a plurality of contacts to the silicide in the plurality of contact holes over the portion of the plurality of S/D regions to reduce capacitance in a partially strapped configuration.

11. A method for forming a salicide, comprising:

forming gate structures with a dummy gate material;

forming, on at least one semiconductor fin, at least one source/drain (S/D) region including a (111) facet and having a cross-sectional quadrilateral shape;

forming a conductive material on the (111) facet;

annealing the conductive material to form a silicide on the (111) facet;

replacing the dummy gate material with a gate conductor after the annealing; and

forming at least one contact to the silicide.

12. The method as recited in claim 11 , wherein the conductive material is formed on a top side of the (111) facet of the at least one S/D region.

13. The method as recited in claim 11 , wherein:

forming the at least one S/D region further includes forming a plurality of S/D regions including (111) facets and having cross-sectional quadrilateral shapes on a plurality of semiconductor fins, the quadrilateral shapes being separated in a non-merged configuration; and

the S/D regions on adjacent ones of the semiconductor fins having separated cross-sectional quadrilateral shapes.

14. The method as recited in claim 13 , wherein the conductive material is formed on all facets of the plurality of S/D regions in a wrapped around configuration.

15. The method as recited in claim 13 , wherein annealing the conductive material further includes forming merged silicides between the plurality of S/D regions.

16. The method as recited in claim 11 , wherein forming the at least one contact further includes:

forming a dielectric layer over the at least one S/D region;

forming at least one contact hole in the dielectric layer; and

forming the at least one contact to the silicide in the at least one contact hole.

17. The method as recited in claim 16 , wherein the at least one S/D region includes a plurality of S/D regions, and wherein forming the at least one contact hole further includes forming a plurality of contact holes over a portion of the plurality of S/D regions.

18. The method as recited in claim 17 , wherein forming the at least one contact further includes forming a plurality of contacts to the silicide in the plurality of contact holes over the portion of the plurality of S/D regions to reduce capacitance in a partially strapped configuration.

19. The method as recited in claim 11 , wherein annealing the conductive material further includes performing a thermally stabilizing anneal process with a laser anneal at a temperature of between about 900 to 1100 degrees C. for less than or equal to 1 millisecond.

20. The method as recited in claim 19 , wherein annealing the conductive material further includes performing an additional anneal process to continue to form the silicide.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE OF THE ASSIGNOR PREVIOUSLY RECORDED ON REEL 050818 FRAME 0633. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Nov 29, 2019
From: ADUSUMILLI, PRANEET; ALPTEKIN, EMRE; LAVOIE, CHRISTIAN; OZCAN, AHMET S.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 051144/0527 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 24, 2019
From: ADUSUMILLI, PRANEET; ALPTEKIN, EMRE; LAVOIE, CHRISTIAN; OZCAN, AHMET
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 050818/0633 →
Continuity (3)
Continuation 15806899 · Nov 8, 2017
Continuation 15492418 · Apr 20, 2017
Related Publication 20200058758A1 · Feb 20, 2020