Technologies for efficiently performing scatter-gather operations
Technologies for efficiently performing scatter-gather operations include a device with circuitry configured to associate, with a template identifier, a set of non-contiguous memory locations of a memory having a cross point architecture. The circuitry is additionally configured to access, in response to a request that identifies the non-contiguous memory locations by the template identifier, the memory locations.
1. A device comprising:
circuitry to:
associate a set of non-contiguous memory locations of a memory having a three dimensional cross point architecture with a template identifier; and
access the non-contiguous memory locations in response to a request that identifies the non-contiguous memory locations by the template identifier, including to access multiple bits at a memory location, wherein each of the multiple bits corresponds with a different layer of the memory at the memory location.
2. The device of claim 1 , wherein to associate a set of non-contiguous memory locations of a memory having a three dimensional cross point architecture with a template identifier comprises to associate a set of column and row identifiers with the template identifier.
3. The device of claim 2 , wherein to associate the set of column and row identifiers with the template identifier comprises to associate a set of column and row coordinates that each represent multiple bits with a template identifier.
4. The device of claim 1 , wherein to associate a set of non-contiguous memory locations of a memory having a three dimensional cross point architecture with a template identifier comprises to receive a request to define a template and associate, in response to the request, the set of non-contiguous memory locations with the template identifier.
5. The device of claim 4 , wherein to receive a request to define the template comprises to receive a request that includes a mask indicative of the set of non-contiguous memory locations to be associated with the template identifier.
6. The device of claim 4 , wherein to receive a request to define the template comprises to receive a request that includes the template identifier to be associated with the set of non-contiguous memory locations.
7. The device of claim 4 , wherein the circuitry is further to provide the template identifier in a response to the request to define the template after the set of non-contiguous memory locations have been associated with the template identifier.
8. The device of claim 1 , wherein to associate the set of non-contiguous memory locations with the template identifier comprises to store the set of non-contiguous memory locations in association with the template identifier in the memory.
9. The device of claim 1 , wherein to access the non-contiguous memory locations comprises to write data to the non-contiguous memory locations.
10. The device of claim 9 , wherein to write data to the non-contiguous memory locations comprises to:
determine the non-contiguous memory locations associated with the template identifier; and
partition a contiguous set of data from the request across the non-contiguous memory locations associated with the template identifier.
11. The device of claim 10 , wherein to determine the non-contiguous memory locations associated with the template identifier comprises to read, from the memory, a set of non-contiguous column and row identifiers associated with the template identifier.
12. The device of claim 10 , wherein to partition the contiguous set of data across the non-contiguous memory locations comprises to write multiple bits of the contiguous set of data to the memory location, wherein each bit corresponds with a different layer of the three dimensional cross point architecture at the memory location.
13. The device of claim 10 , wherein to partition the contiguous set of data across the non-contiguous memory locations comprises to write multiple bits associated with image data to the memory location.
14. The device of claim 10 , wherein to partition the contiguous set of data across the non-contiguous memory locations comprises to write, to the memory location, multiple bits indicative of a pointer to another location.
15. The device of claim 1 , wherein to access the non-contiguous memory locations comprises to read data from the non-contiguous memory locations.
16. The device of claim 15 , wherein to read data from the non-contiguous memory locations comprises to:
determine the non-contiguous memory locations associated with the template identifier; and
concatenate the data from the non-contiguous memory locations into a contiguous array.
17. The device of claim 15 , wherein to read data from the non-contiguous memory locations comprises to read multiple bits from the memory location, wherein each bit corresponds with a different layer of the three dimensional cross point architecture.
18. A method comprising:
associating, by a device, a set of non-contiguous memory locations of a memory having a three dimensional cross point architecture with a template identifier; and
accessing, by the device and in response to a request that identifies the non-contiguous memory locations by the template identifier, the non-contiguous memory locations, including to access multiple bits at a memory location, wherein each of the multiple bits corresponds with a different layer of the memory at the memory location.
19. One or more machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause a device to:
associate a set of non-contiguous memory locations of a memory having a three dimensional cross point architecture with a template identifier; and
access the non-contiguous memory locations in response to a request that identifies the non-contiguous memory locations by the template identifier, including to access multiple bits at a memory location, wherein each of the multiple bits corresponds with a different layer of the memory at the memory location.