Systems including memory cells on opposing sides of a pillar
Systems including a processor and a memory device in communication with the processor include an array of non-volatile memory cells configured in a NAND architecture. The array includes a plurality of series-coupled first non-volatile memory cells, each first non-volatile memory cell curving around a first curved side of a substantially vertical pillar and terminating at an isolation region, and a plurality of series-coupled second non-volatile memory cells, each second non-volatile memory cell curving around a second curved side of the substantially vertical pillar and terminating at the isolation region. Respective ones of the first non-volatile memory cells are respectively at same vertical levels as respective ones of the second non-volatile memory cells.
1. A system, comprising:
a processor; and
a memory device in communication with the processor, wherein the memory device comprises an array of non-volatile memory cells configured in a NAND architecture, the array of non-volatile memory cells comprising:
a plurality of series-coupled first non-volatile memory cells, each first non-volatile memory cell of the plurality of series-coupled first non-volatile memory cells curving around a first curved side of a substantially vertical pillar and terminating at a first isolation region in contact with the substantially vertical pillar and at a second isolation region in contact with the substantially vertical pillar, wherein the substantially vertical pillar is between the first isolation region and the second isolation region;
a plurality of series-coupled second non-volatile memory cells, different than the plurality of series-coupled first non-volatile memory cells, each second non-volatile memory cell of the plurality of series-coupled second non-volatile memory cells curving around a second curved side of the substantially vertical pillar and terminating at the first isolation region and at the second isolation region, wherein the first isolation region and the second isolation region are each between the plurality of series-coupled first non-volatile memory cells and the plurality of series-coupled second non-volatile memory cells;
wherein respective ones of the first non-volatile memory cells of the plurality of series-coupled first non-volatile memory cells are respectively at same vertical levels as respective ones of the second non-volatile memory cells of the plurality of series-coupled second non-volatile memory cells.
2. The system of claim 1 , wherein the array of non-volatile memory cells further comprises a select transistor that selectively couples the plurality of series-coupled first non-volatile memory cells and the plurality of series-coupled second non-volatile memory cells to a source.
3. The system of claim 2 , wherein the select transistor comprises a channel that is coupled to the substantially vertical pillar and the source.
4. The system of claim 1 , wherein the array of non-volatile memory cells further comprises a select transistor that selectively couples the plurality of series-coupled first non-volatile memory cells and the plurality of series-coupled second non-volatile memory cells to a data line.
5. The system of claim 4 , wherein the select transistor comprises a channel that is coupled to the substantially vertical pillar and the data line.
6. The system of claim 1 , wherein the substantially vertical pillar comprises a semiconductor.
7. The system of claim 1 , wherein each of the plurality of series-coupled first non-volatile memory cells and each of the plurality of series-coupled second non-volatile memory cells is a semiconductor-oxide-nitride-oxide-semiconductor memory cell.
8. The system of claim 1 , wherein the array of non-volatile memory cells configured in a NAND architecture comprises an array of non-volatile memory cells configured in a three-dimensional NAND architecture.
9. A system, comprising:
a processor; and
a memory device in communication with the processor, wherein the memory device comprises an array of non-volatile memory cells configured in a NAND architecture, the array of non-volatile memory cells comprising:
a conductive pillar;
a plurality of first non-volatile memory cells on a first side of the conductive pillar coupled in series by the conductive pillar, each first non-volatile memory cell of the plurality of first non-volatile memory cells comprising a respective portion of the first side of the conductive pillar, a respective portion of a first charge trap adjacent to the first side of conductive pillar and a respective first control gate adjacent to the respective portion of the first charge trap;
a plurality of second non-volatile memory cells on a second side of the conductive pillar, opposite to the first side of the conductive pillar, coupled in series by the conductive pillar, each second non-volatile memory cell of the plurality of second non-volatile memory cells comprising a respective portion of the second side of the conductive pillar, a respective portion of a second charge trap adjacent to the second side of the conductive pillar and a respective second control gate adjacent to the respective portion of the second charge trap; and
a single select transistor that selectively couples the plurality of first non-volatile memory cells and the plurality of second non-volatile memory cells to one of a source line and a data line;
wherein each first control gate of the plurality of first non-volatile memory cells is electrically isolated from each second control gate of the plurality of second non-volatile memory cells; and
wherein respective ones of the first non-volatile memory cells of the plurality of first non-volatile memory cells are respectively at same vertical levels as respective ones of the second non-volatile memory cells of the plurality of second non-volatile memory cells.
10. The system of claim 9 , wherein each first charge trap of the plurality of first non-volatile memory cells is electrically isolated from each second charge trap of the plurality of second non-volatile memory cells.
11. The system of claim 9 , wherein the conductive pillar is a first conductive pillar, and wherein the single select transistor is adjacent to a second conductive pillar coupled to the first conductive pillar.
12. The system of claim 9 , wherein the conductive pillar forms a channel for both the plurality of first non-volatile memory cells and the plurality of second non-volatile memory cells.
13. A system, comprising:
a processor; and
a memory device in communication with the processor, wherein the memory device comprises an array of non-volatile memory cells configured in a NAND architecture, the array of non-volatile memory cells comprising:
a first pair of electrically isolated activation lines formed on opposing sides of one or more conductive pillars, wherein a first one of the first pair of electrically isolated activation lines is electrically isolated from a second one of the first pair of electrically isolated activation lines;
a second pair of electrically isolated activation lines formed on opposing sides of the one or more conductive pillars, wherein a first one of the second pair of electrically isolated activation lines is electrically isolated from a second one of the second pair of electrically isolated activation lines; and
a plurality of charge storage nodes, wherein each charge storage node of the plurality of charge storage nodes is interposed between a respective conductive pillar of the one or more conductive pillars and a respective activation line of first pair of electrically isolated activation lines or the second pair of electrically isolated activation lines;
wherein a non-volatile memory cell formed at an intersection of the first one of the first pair of electrically isolated activation lines and a given one of the conductive pillars, and a non-volatile memory cell formed at an intersection of the first one of the second pair of electrically isolated activation lines and the given one of the conductive pillars, form at least a portion of a first serially-coupled string of non-volatile memory cells comprising a first portion of the given one of the conductive pillars;
wherein a non-volatile memory cell formed at an intersection of the second one of the first pair of electrically isolated activation lines and the given one of the conductive pillars, and a non-volatile memory cell formed at an intersection of the second one of the second pair of electrically isolated activation lines and the given one of the conductive pillars, form at least a portion of a second serially-coupled string of non-volatile memory cells comprising a second portion of the given one of the conductive pillars; and
wherein the first one of the first pair of electrically isolated activation lines and the first one of the second pair of electrically isolated activation lines are formed on the same side of the given one of the conductive pillars.
14. The system of claim 13 , further comprising a first select transistor coupled to a first end of the first serially-coupled string of non-volatile memory cells and a first end of the second serially-coupled string of non-volatile memory cells.
15. The system of claim 14 , wherein the one or more conductive pillars are one or more first conductive pillars, wherein the first select transistor is formed at an intersection between a select line and a second conductive pillar coupled to an end of the given one of the first conductive pillars.
16. The system of claim 15 , wherein second conductive pillar is further coupled to a source line.
17. The system of claim 14 further comprises a second select transistor coupled to a second end of the first serially-coupled string of non-volatile memory cells and a second end of the second serially-coupled string of non-volatile memory cells.
18. The system of claim 17 , wherein the one or more conductive pillars are one or more first conductive pillars, wherein the second select transistor is formed at an intersection between a select line and a second conductive pillar coupled to a second end of the given one of the first conductive pillars.
19. The system of claim 18 , wherein second conductive pillar is further coupled to a data line.
20. The system of claim 17 , wherein the first select transistor selectively couples the first serially-coupled string of non-volatile memory cells and the second serially-coupled string of non-volatile memory cells to a source line and the second select transistor selectively couples the first serially-coupled string of non-volatile memory cells and the second serially-coupled string of non-volatile memory cells to a data line.
21. The system of claim 13 , further comprising an isolation region interposed between the first and second ones of the first and second pairs of electrically isolated activation lines.
22. The system of claim 21 , wherein the isolation region extends between the charge storage node interposed between the first one of the first pair of electrically isolated activation lines and the given one of the conductive pillars and the charge storage node interposed between the second one of the first pair of electrically isolated activation lines and the given one of the conductive pillars.
23. The system of claim 22 , wherein the isolation region further extends between the charge storage node interposed between the first one of the second pair of electrically isolated activation lines and the given one of the conductive pillars and the charge storage node interposed between the second one of the second pair of electrically isolated activation lines and the given one of the conductive pillars.