Semiconductor device
A polycrystalline silicon resistor is large in coefficient of fluctuation in resistance between before and after the completion of a package molding process. To enable highly accurate trimming, it is desired to implement a resistor that is hardly subjected to stress produced in a substrate during a package molding process. A resistance element is formed of a plurality of wiring layers and has a repetitive pattern of a first conductive layer formed in a first wiring layer, a second conductive layer formed in a second wiring layer, and an interlayer conductive layer coupling the first conductive layer and the second conductive layer together.
1. A semiconductor device comprising:
a semiconductor substrate; and
a plurality of wiring layers formed over the semiconductor substrate and including at least a first wiring layer and a second wiring layer,
wherein a resistance element is formed in the wiring layers, and
wherein the resistance element has a repetitive pattern of a first conductive layer formed in the first wiring layer, a second conductive layer formed in the second wiring layer, and an interlayer conductive layer coupling the first conductive layer and the second conductive layer together,
wherein a resistance value of the interlayer conductive layer is greater than the sum of a resistance value of the first conductive layer and a resistance value of the second conductive layer.
2. The semiconductor device according to claim 1 ,
wherein the interlayer conductive layer includes a metal layer or a polysilicon layer formed between the first conductive layer and the second conductive layer.
3. The semiconductor device according to claim 1 ,
wherein the wiring layers include a third wiring layer between the first wiring layer and the second wiring layer, and
wherein the interlayer conductive layer includes a landing PAD formed in the third wiring layer, a first via coupling the first conductive layer and the landing PAD together, and a second via coupling the second conductive layer and the landing PAD together.
4. The semiconductor device according to claim 3 ,
wherein in the first via and the second via, a buried layer obtained by burying a W layer in a TiN layer is formed.
5. The semiconductor device according to claim 1 ,
wherein in the first wiring layer, the lengthwise direction of the first conductive layer is taken as a first direction and a direction perpendicular to the first direction is taken as a second direction, and
wherein a plurality of the interlayer conductive layers included in the resistance element are arranged in a matrix pattern in the first direction and the second direction.
6. The semiconductor device according to claim 5 ,
wherein the interlayer conductive layers included in the resistance element and adjoining to each other are disposed with a minimum interval of vias in the semiconductor device.
7. The semiconductor device according to claim 1 , comprising:
a trimming circuit using a plurality of the resistance elements.
8. A semiconductor device comprising:
a semiconductor substrate;
a plurality of wiring layers formed over the semiconductor substrate, and
a trimming circuit including resistance elements formed in the wiring layers,
wherein the wiring layers include at least a first wiring layer and a second wiring layer, and
wherein the resistance element includes a repetitive pattern of a first conductive layer formed in the first wiring layer, a second conductive layer formed in the second wiring layer, and an interlayer conductive layer coupling the first conductive layer and the second conductive layer together,
wherein a resistance value of the interlayer conductive layer is greater than the sum of a resistance value of the first conductive layer and a resistance value of the second conductive layer.
9. The semiconductor device according to claim 8 ,
wherein the trimming circuit includes a plurality of the resistance elements coupled in series and a switch coupled in parallel with each of the resistance elements.
10. The semiconductor device according to claim 8 ,
wherein the interlayer conductive layer includes a metal layer or a polysilicon layer formed between the first conductive layer and the second conductive layer.
11. The semiconductor device according to claim 8 ,
wherein the wiring layers include a third wiring layer between the first wiring layer and the second wiring layer, and
wherein the interlayer conductive layer includes a landing PAD formed in the third wiring layer, a first via coupling the first conductive layer and the landing PAD together, and a second via coupling the second conductive layer and the landing PAD together.
12. The semiconductor device according to claim 8 ,
wherein in the first wiring layer, the lengthwise direction of the first conductive layer is taken as a first direction and a direction perpendicular to the first direction is taken as a second direction, and
wherein a plurality of the interlayer conductive layers included in the resistance element are arranged in a matrix pattern in the first direction and the second direction.
13. The semiconductor device according to claim 12 ,
wherein the interlayer conductive layers included in the resistance element and adjoining to each other are arranged with a minimum interval of vias in the semiconductor device.
14. The semiconductor device according to claim 1 , wherein the plurality of wiring layers and has a main resistance in a direction perpendicular to a plane of the semiconductor substrate where a semiconductor element is formed.
15. The semiconductor device according to claim 1 , wherein the interlayer conductive layer is formed perpendicular with the first conductive layer, the second conductive layer, and a plane of the semiconductor substrate.
16. A semiconductor device comprising:
a semiconductor substrate; and
a plurality of wiring layers formed over the semiconductor substrate and including at least a first wiring layer and a second wiring layer,
wherein a resistance element is formed in the wiring layers,
wherein the resistance element includes a first conductive layer formed in the first wiring layer, a second conductive layer formed in the second wiring layer, and an interlayer conductive layer coupling the first conductive layer and the second conductive layer together, and
wherein a resistance value of the interlayer conductive layer is greater than the sum of a resistance value of the first conductive layer and a resistance value of the second conductive layer.
17. The semiconductor device according to claim 16 ,
wherein the plurality of wiring layers and has a main resistance in a direction perpendicular to a plane of the semiconductor substrate where a semiconductor element is formed.
18. The semiconductor device according to claim 16 ,
wherein the interlayer conductive layer includes a metal layer or a polysilicon layer formed between the first conductive layer and the second conductive layer, and
wherein the interlayer conductive layer is formed perpendicular with the first conductive layer, the second conductive layer, and a plane of the semiconductor substrate.