Semiconductor package and method of manufacturing the same

1. A method of manufacturing a semiconductor package, the method comprising:

providing a carrier substrate having a first trench formed on a first top surface of the carrier substrate;

providing an adhesive layer on the first top surface of the carrier substrate, the adhesive layer having a second trench that corresponds to the first trench;

providing a first semiconductor chip on the carrier substrate;

mounting at least one second semiconductor chip on a second top surface of the first semiconductor chip;

coating a mold member to fill the second trench, and surround a first lateral surface of the first semiconductor chip and a second lateral surface of the at least one second semiconductor chip; and

curing the mold member to form a mold layer,

wherein the first trench is provided along a first edge of the first semiconductor chip,

wherein the mold member covers a second edge of a bottom surface of the first semiconductor chip, and

wherein the bottom surface of the first semiconductor chip is substantially in parallel with the second top surface of the first semiconductor chip.

2. The method of claim 1 , wherein, when the mold member is coated, the mold member is introduced toward the first trench.

3. The method of claim 2 , wherein a first portion of the first trench overlaps the first edge of the first semiconductor chip, and

wherein a second portion of the first trench hangs outside the first edge of the first semiconductor chip.

4. The method of claim 2 , wherein the first semiconductor chip comprises a plurality of connection terminals provided on the bottom surface of the first semiconductor chip.

5. The method of claim 4 , wherein the adhesive layer comprises a concave portion vertically overlapping the first trench, and

wherein, when the mold member is coated, the mold member fills the concave portion.

6. The method of claim 5 , wherein a depth of the concave portion is 0.1 to 0.5 times a height of the plurality of connection terminals.

7. The method of claim 4 , wherein the mold member is spaced apart from the plurality of connection terminals.

8. The method of claim 1 , wherein a cross-section of the first trench has at least one of a tetragonal shape, a semicircular shape, and a triangular shape, and

wherein the semicircular shape and the triangular shape have a width that decreases from the first top surface of the carrier substrate toward an interior of the carrier substrate.

9. The method of claim 1 , wherein the first trench comprises:

a first portion extending in a first direction parallel to the first top surface of the carrier substrate; and

a second portion extending in a second direction parallel to the first top surface of the carrier substrate, the second direction intersecting the first direction.

10. The method of claim 9 , wherein the first trench further comprises a third portion adjacent to an intersection of the first portion and the second portion, the third portion overlapping a corner of the first semiconductor chip when viewed in plan.

11. The method of claim 1 , further comprising removing a portion of the carrier substrate before forming the mold layer.

12. The method of claim 1 , wherein the mold layer comprises:

a first segment surrounding the first lateral surface of the first semiconductor chip and the second lateral surface of the at least one second semiconductor chip; and

a second segment extending from a bottom end of the first segment and covering the second edge of the bottom surface of the first semiconductor chip.