Integrated circuit layout method, device, and system
A method includes positioning a first active region adjacent to a pair of second active regions in an initial integrated circuit (IC) layout diagram of an initial cell, to align side edges of the first active region and corresponding side edges of each second active region of the pair of second active regions along a cell height direction. The method further includes arranging at least one first fin feature in the first active region, to obtain a modified cell having a modified IC layout diagram. The side edges of the first active region and the corresponding side edges of each second active region extend along the cell height direction. A height dimension of the first active region in the cell height direction is less than half of a height dimension of each second active region of the pair of second active regions in the cell height direction. At least one of the positioning the first active region or the arranging the at least one first fin feature is executed by a processor.
1. An integrated circuit (IC) device, comprising:
a first active region;
a pair of second active regions adjacent to the first active region, wherein side edges of the first active region and corresponding side edges of each second active region of the pair of second active regions are aligned along a cell height direction; and
at least one first fin feature in the first active region,
wherein
the side edges of the first active region and the corresponding side edges of each second active region extend along the cell height direction, and
a height dimension of the first active region in the cell height direction is less than half of a height dimension of each second active region of the pair of second active regions in the cell height direction.
2. The IC device of claim 1 , wherein
the pair of second active regions form a first cell,
the first cell and the first active region form a second cell, and
the second cell has a cell height dimension in the cell height direction corresponding to 2.5 times a standard cell height dimension.
3. The IC device of claim 2 , wherein
the first cell has a cell height dimension in the cell height direction corresponding to twice the standard cell height dimension.
4. The IC device of claim 2 , wherein
the first cell corresponds to a standard cell obtainable from a cell library.
5. The IC device of claim 2 , wherein
the second cell corresponds to a standard cell obtainable from a cell library.
6. The IC device of claim 1 , wherein
the second active regions of the pair of second active regions are different type active regions, and
the first active region and a closer second active region of the pair of second active regions are different type active regions.
7. The IC device of claim 1 , further comprising:
a third active region adjacent to the pair of second active regions, wherein the side edges of the first active region, the corresponding side edges of each second active region of the pair of second active regions, and corresponding side edges of the third active region are aligned along the cell height direction; and
at least one second fin feature in the third active region,
wherein
the corresponding side edges of the third active region extend along the cell height direction, and
a height dimension of the third active region in the cell height direction is the same as the height dimension of the first active region in the cell height direction.
8. The IC device of claim 7 , wherein
the first and third active regions are on opposite sides of the pair of second active regions along the cell height direction.
9. The IC device of claim 8 , wherein
the second active regions of the pair of second active regions are different type active regions,
the first active region and a closer second active region of the pair of second active regions are different type active regions, and
the first active region and the third active region are different type active regions.
10. The IC device of claim 1 , wherein
the at least one first fin feature in the first active region configures at least one of a function cell, a physical cell, an engineering change order (ECO) cell, or a filler cell over the first active region.
11. An integrated circuit (IC) device, comprising:
a cell;
first one or more adjacent cells; and
second one or more adjacent cells,
wherein
along a cell width direction,
a top edge of a first active region of the cell is aligned with a top edge of one active region of a pair of first adjacent active regions of the first one or more adjacent cells, and
a bottom edge of the first active region of the cell is aligned with a bottom edge of another active region of the pair of first adjacent active regions,
a distance in a cell height direction between the top edge of the one active region and the bottom edge of the another active region in the pair of first adjacent active regions is equal to a height dimension of the first active region in the cell height direction,
along the cell width direction,
a top edge of a second active region of the cell is aligned with a top edge of one active region of a pair of second adjacent active regions of the second one or more adjacent cells, and
a bottom edge of the second active region of the cell is aligned with a bottom edge of another active region of the pair of second adjacent active regions,
a distance in the cell height direction between the top edge of the one active region and the bottom edge of the another active region in the pair of second adjacent active regions is equal to a height dimension of the second active region in the cell height direction, and
along the cell width direction,
a top edge of a third active region of the cell is aligned with a top edge of a third adjacent active region of one of the first one or more adjacent cells or the second one or more adjacent cells, and
a bottom edge of the third active region of the cell is aligned with a bottom edge of the third adjacent active region.
12. The IC device of claim 11 , wherein
the first active region and each active region of the pair of first adjacent active regions are each a first type active region, and
the second active region and each active region of the pair of second adjacent active regions are each a second type active region different from the first type active region.
13. The IC device of claim 12 , wherein
the third active region and the third adjacent active region are each a first type active region, or
the third active region and the third adjacent active region are each a second type active region.
14. The IC device of claim 11 , wherein
along the cell width direction, the top and bottom edges of the third active region of the cell are correspondingly aligned with the top and bottom edges of the third adjacent active region of one of the second one or more adjacent cells, and
along the cell width direction,
a top edge of a fourth active region of the cell is aligned with a top edge of a fourth adjacent active region of one of the first one or more adjacent cells, and
a bottom edge of the fourth active region of the cell is aligned with a bottom edge of the fourth adjacent active region.
15. The IC device of claim 14 , wherein
the first active region and each active region of the pair of first adjacent active regions are each a first type active region,
the second active region and each active region of the pair of second adjacent active regions are each a second type active region different from the first type active region,
the third active region and the third adjacent active region are each a first type active region, and
the fourth active region and the fourth adjacent active region are each a second type active region.
16. An integrated circuit (IC) device, comprising:
a high performance computing (HPC) cell comprising first, second and third active regions; and
a plurality of adjacent cells arranged
consecutively along a cell height direction, and
adjacent to the HPC cell and on a same side of the HPC cell in a cell width direction,
wherein
a top edge of the first active region of the HPC cell is aligned, along the cell width direction, with a top edge of one active region of a pair of first adjacent active regions correspondingly belonging to first and second adjacent cells among the plurality of adjacent cells,
a bottom edge of the first active region of the HPC cell is aligned, along the cell width direction, with a bottom edge of another active region of the pair of first adjacent active regions,
a distance in the cell height direction between the top edge of the one active region and the bottom edge of the another active region in the pair of first adjacent active regions is equal to a height dimension of the first active region in the cell height direction,
a top edge of the second active region of the HPC cell is aligned, along the cell width direction, with a top edge of one active region of a pair of second adjacent active regions at least one of which belongs to the second adjacent cell,
a bottom edge of the second active region of the HPC cell is aligned, along the cell width direction, with a bottom edge of another active region of the pair of second adjacent active regions,
a distance in the cell height direction between the top edge of the one active region and the bottom edge of the another active region in the pair of second adjacent active regions is equal to a height dimension of the second active region in the cell height direction,
a top edge of the third active region of the HPC cell is aligned, along the cell width direction, with a top edge of a third adjacent active region belonging to one of the first adjacent cell or the second adjacent cell, and
a bottom edge of the third active region of the HPC cell is aligned, along the cell width direction, with a bottom edge of the third adjacent active region.
17. The IC device of claim 16 , wherein
the plurality of adjacent cells further comprises a third adjacent cell,
the second adjacent cell is adjacent to and between the first and third adjacent cells, and
one active region of the pair of second adjacent active regions belongs to the second adjacent cell, and the other active region of the pair of second adjacent active regions belongs to the first adjacent cell.
18. The IC device of claim 17 , wherein
the HPC cell further comprises a fourth active region having
a top edge which is aligned, along the cell width direction, with a top edge of a fourth adjacent active region belonging to one of the first adjacent cell or the third adjacent cell, and
a bottom edge which is aligned, along the cell width direction, with a bottom edge of the fourth adjacent active region.
19. The IC device of claim 16 , wherein
both active regions of the pair of second adjacent active regions belong to the second adjacent cell.
20. The IC device of claim 19 , wherein
the HPC cell further comprises a fourth active region having
a top edge which is aligned, along the cell width direction, with a top edge of a fourth adjacent active region belonging to the other one of the first adjacent cell or the second adjacent cell, and
a bottom edge which is aligned, along the cell width direction, with a bottom edge of the fourth adjacent active region.