VHSA-VDDSA generator merging scheme
A memory device is provided including physical block circuitry including a first lateral network arrangement and a second lateral network arrangement. Each of the first and second lateral network arrangements includes a single generator configured to output both a sense amplifier voltage VHSA and a data latch voltage VDDSA, in each of a first mode and a second mode. In the first mode, during which read and program verify and other operations may occur, the generator receives VHSA as a feedback signal and in the second mode, during which programming, POR, and EVFY operations may occur, the generator receives VDDSA as a feedback signal.
1. A memory device comprising:
a memory array; and
physical block circuitry, comprising a first lateral network arrangement and a second lateral network arrangement, each comprising:
a generator configured to output a sense amplifier voltage VHSA and a data latch voltage VDDSA in each of a first mode and a second mode;
wherein, in the first mode, the generator receives VHSA as a feedback signal and in the second mode, the generator receives VDDSA as a feedback signal.
2. The memory device according to claim 1 , wherein the peripheral block circuitry is configured to perform a read operation and a program verify operation on the memory array in the first mode.
3. The memory device according to claim 1 , wherein the peripheral block circuitry is configured to perform a programming operation on the memory array in the second mode.
4. The memory device according to claim 1 , wherein each of the first lateral network arrangement and the second lateral network arrangement further comprises a multiplexer configured to output a data latch programming signal in the first mode and to output an external voltage in the second mode.
5. The memory device according to claim 1 , wherein each of the first lateral network arrangement and the second lateral network arrangement further comprises a multiplexer which outputs VHSA to the generator in the first mode and outputs VDDSA to the generator in the second mode.
6. The memory device according to claim 1 , wherein each of the first lateral network arrangement and the second lateral network arrangement further comprises a current limiter configured to be disabled in the first mode and configured to supply a voltage to a bit line of the memory array during a program operation in the second mode.
7. A lateral network arrangement of a memory device, the lateral network arrangement comprising:
a generator configured to output a sense amplifier voltage VHSA and a data latch voltage VDDSA in each of a first mode and a second mode;
wherein, in the first mode, the generator receives VHSA as a feedback signal and in the second mode, the generator receives VDDSA as a feedback signal.
8. The lateral network arrangement of claim 6 , further comprising a multiplexer configured to output a data latch programming signal in the first mode and to output an external voltage in the second mode.
9. The lateral network arrangement of claim 6 , further comprising a current limiter configured to be disabled in the first mode and configured to supply a voltage to a bit line of the memory array during the program operation in the second mode.
10. Physical block circuitry of a memory device, the physical block circuitry comprising:
peripheral circuitry;
a first lateral network arrangement and a second lateral network arrangement, each comprising:
a generator configured to output a sense amplifier voltage VHSA and a data latch voltage VDDSA in each of a first mode and a second mode;
wherein, in the first mode, the generator receives VHSA as a feedback signal and in the second mode, the generator receives VDDSA as a feedback signal.
11. The memory device according to claim 10 , wherein the peripheral block circuitry is configured to perform a read operation and a program verify operation on a memory array of the memory device in the second mode.
12. The memory device according to claim 10 , wherein the peripheral block circuitry is configured to perform a programming operation on a memory array of the memory device in the first mode.
13. The memory device according to claim 10 , wherein each of the first lateral network arrangement and the second lateral network arrangement further comprises a multiplexer configured to output a data latch programming signal in the first mode and to output an external voltage in the second mode.
14. The memory device according to claim 10 , wherein each of the first lateral network arrangement and the second lateral network arrangement further comprises a multiplexer which outputs VHSA to the generator in the first mode and outputs VDDSA to the generator in the second mode.
15. The memory device according to claim 10 , wherein each of the first lateral network arrangement and the second lateral network arrangement further comprises a current limiter configured to be disabled in the first mode and configured to supply a voltage to a bit line of the memory array during a program operation in the second mode.