IP Library Granted Patent US 10,971,401
Granted Patent B2
US 10,971,401 · App. 16/593,831 · Granted Apr 6, 2021

Systems and methods for precision fabrication of an orifice within an integrated circuit

Inventor: Jean-Philippe Fricker (Los Altos, CA)
Assignee: Cerebras Systems Inc.
H01L21/78H01L21/02019H01L21/0475H01L21/3043H01L21/30604H01L21/76802B23K26/384H01L21/3065H01L21/3105
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Quick Facts
Patent No.
US 10,971,401
App. No.
16/593,831
Granted
Apr 6, 2021
Kind
B2
Abstract

A method for fabricating an orifice in a semiconductor which can include: removing a first depth of the semiconductor using a first material removal technique and removing a second depth of the semiconductor using a second material removal technique. The method can optionally include: adding a sacrificial layer of material and reducing a depth of the semiconductor by a friction-based material removal technique. In examples, the method fabricates a wafer-scale processor with a set of fastening features.

Claims (34)

1. A method comprising:

adding a sacrificial layer to a first surface of a semiconductor substrate; and

along an orifice axis normal to the first surface, subsequently:

fabricating a cavity in the semiconductor substrate using a first material removal technique, the cavity comprising a first radius about the orifice axis and a first depth along the orifice axis; and

subsequently fabricating an orifice in the semiconductor substrate using a second material removal technique, the orifice comprising a second radius about the orifice axis, the orifice extending from the first depth, along the orifice axis, wherein the second radial distance defines a diameter of about 2 millimeters, wherein the second radius has a second radial distance that is smaller than a first radial distance of first radius,

wherein the first and second material removal techniques remove material in the same direction along the orifice axis.

2. The method according to claim 1 , wherein

fabricating the cavity comprises removing at least a radial section of the sacrificial layer and a radial section of a metal layer formed at the first surface of the semiconductor substrate.

3. The method according to claim 2 , wherein

fabricating the cavity further comprises removing a radial section of dielectric material from the semiconductor substrate.

4. The method according to claim 1 , wherein:

the second material removal technique is different from the first material removal technique.

5. The method according to claim 4 , wherein

the first material removal technique comprises laser ablation.

6. The method according to claim 5 , wherein

the second material removal technique comprises chemical etching.

7. The method according to claim 1 , wherein:

the first depth comprises a full depth of a metal layer of the semiconductor substrate and a partial depth of a silicon layer of the semiconductor substrate.

8. The method according to claim 1 , wherein

fabricating the cavity in the semiconductor substrate using a first material removal technique comprises:

removing the first depth of material of the semiconductor substrate that includes an active circuitry layer of material until a silicon layer of material of the semiconductor substrate that is arranged beyond the first depth of material is exposed.

9. The method according to claim 1 , further comprising:

removing the sacrificial layer of material along an entirety of the first surface of the semiconductor substrate after fabricating the cavity.

10. The method according to claim 1 , wherein:

fabricating the orifice further comprises reducing a depth of the semiconductor substrate along a second surface of the semiconductor substrate that is opposite the first surface of the semiconductor substrate thereby exposing a through-hole cooperatively fabricated by the first and second material removal techniques.

11. The method according to claim 1 , further comprising

in advance of fabricating the orifice, removing a plurality of trenches of material along a second surface of the semiconductor substrate that is opposite the first surface of the semiconductor substrate.

12. The method according to claim 1 , wherein

before fabricating the cavity, the semiconductor substrate comprises a first composition of material along the orifice axis up to the first depth that is different from a second composition of material of the semiconductor substrate along the orifice axis at the second depth.

13. The method according to claim 1 , wherein:

adding the sacrificial layer to the first surface of the semiconductor substrate includes:

depositing a coating of sacrificial material onto a first surface that includes an active circuitry layer of the semiconductor substrate.

14. The method according to claim 1 , wherein:

the second depth is greater than the first depth.

Assignments (2)
SECURITY INTEREST Recorded Jun 18, 2026
From: CEREBRAS SYSTEMS INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS THE COLLATERAL AGENT
Reel/Frame 075845/0844 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 8, 2019
From: FRICKER, JEAN-PHILIPPE
To: CEREBRAS SYSTEMS INC.
Reel/Frame 050658/0554 →
Continuity (2)
Provisional Application 62746432 · Oct 16, 2018
Related Publication 20200118826A1 · Apr 16, 2020