Image sensors
An image sensor includes a semiconductor substrate including a pixel region and a pad region, a plurality of photoelectric conversion regions in the pixel region, an interconnect structure on a front surface of the semiconductor substrate, a pad structure in the pad region and on a rear surface of the semiconductor substrate, a through via structure in the pad region and electrically connected to the interconnect structure through the semiconductor substrate, and an isolation structure at least partially extending through the pad region of the semiconductor substrate from the rear surface of the semiconductor substrate. The isolation structure surrounds the pad structure and the through via structure in a plane extending parallel to the rear surface of the semiconductor substrate.
1. An image sensor comprising:
a semiconductor substrate including a pixel region and a pad region;
a plurality of photoelectric conversion regions in the pixel region;
an interconnect structure on a front surface of the semiconductor substrate;
a pad structure in the pad region, the pad structure on a rear surface of the semiconductor substrate;
at least two through via structures in the pad region, each of the at least two through via structures electrically connected to the interconnect structure through the semiconductor substrate; and
an isolation structure at least partially extending into the semiconductor substrate and through the pad region of the semiconductor substrate from the rear surface of the semiconductor substrate, in a direction extending perpendicular to the rear surface of the semiconductor substrate, the isolation structure surrounding all of the pad structure and all of the at least two through via structures in a plane extending parallel to the rear surface of the semiconductor substrate.
2. The image sensor of claim 1 , wherein
the isolation structure at least partially defines an isolation region in the semiconductor substrate, and
the isolation region and the pad structure overlap each other in the direction extending perpendicular to the rear surface of the semiconductor substrate.
3. The image sensor of claim 1 , wherein
the isolation structure is not between the pad structure and the at least two through via structures within the semiconductor substrate, and
the isolation structure is not between two adjacent through via structures of the at least two through via structures within the semiconductor substrate.
4. The image sensor of claim 1 , wherein the pad structure comprises:
a pad insulation layer extending conformally on an internal wall of a pad trench extending into the semiconductor substrate from the rear surface of the semiconductor substrate; and
a pad conductive layer on the pad insulation layer, the pad conductive layer filling the pad trench.
5. The image sensor of claim 4 , wherein
the at least two through via structures are spaced apart from the pad structure in a direction parallel with the rear surface of the semiconductor substrate,
each of the at least two through via structures includes a via conductive layer on an internal wall of a through via trench, the through via trench extending through the semiconductor substrate, the via conductive layer isolated from direct contact with the pad trench, and
a portion of the pad conductive layer extends onto the rear surface of the semiconductor substrate and is connected to the via conductive layer.
6. The image sensor of claim 4 , wherein
the at least two through via structures overlap the pad structure in the direction extending perpendicular to the rear surface of the semiconductor substrate, and
each of the at least two through via structures includes a via conductive layer on an internal wall of a through via trench, the via conductive layer connected to the pad trench, the via conductive layer connected to the pad conductive layer.
7. The image sensor of claim 1 , further comprising:
a pixel isolation region between two adjacent ones of the plurality of photoelectric conversion regions, the pixel isolation region being on an internal wall of a pixel isolation trench,
wherein the pixel isolation trench extends into the semiconductor substrate from the rear surface of the semiconductor substrate toward the front surface of the semiconductor substrate, and
the pixel isolation trench does not completely penetrate the semiconductor substrate.
8. The image sensor of claim 7 , wherein
the isolation structure has a sidewall inclined at a first angle with respect to the rear surface of the semiconductor substrate,
the pixel isolation region has a sidewall inclined at a second angle with respect to the rear surface of the semiconductor substrate, and the second angle is the same as the first angle.
9. The image sensor of claim 1 , further comprising:
a pixel isolation region between two adjacent ones of the plurality of photoelectric conversion regions, the pixel isolation region being on an internal wall of a pixel isolation trench,
wherein the pixel isolation trench penetrates the semiconductor substrate from the front surface of the semiconductor substrate toward the rear surface of the semiconductor substrate, and
the pixel isolation region extends in the pixel isolation trench from the front surface of the semiconductor substrate toward the rear surface of the semiconductor substrate.
10. The image sensor of claim 9 , wherein the pixel isolation region comprises:
a pixel isolation layer on the internal wall of the pixel isolation trench; and
a pixel isolation conductive layer on the pixel isolation layer, the pixel isolation conductive layer filling the pixel isolation trench.
11. An image sensor comprising:
a semiconductor substrate including a pixel region and a pad region;
a plurality of photoelectric conversion regions in the pixel region;
a pixel isolation region between two adjacent ones of the plurality of photoelectric conversion regions, the pixel isolation region at least partially extending from a rear surface of the semiconductor substrate;
an interconnect structure on a front surface of the semiconductor substrate;
a pad structure in the pad region, the pad structure on the rear surface of the semiconductor substrate;
at least two through via structures in the pad region, each of the at least two through via structures electrically connected to the interconnect structure through the semiconductor substrate; and
an isolation structure at least partially extending into the semiconductor substrate and through the pad region of the semiconductor substrate from the rear surface of the semiconductor substrate, in a direction extending perpendicular to the rear surface of the semiconductor substrate, the isolation structure surrounding the pad structure and the at least two through via structures.
12. The image sensor of claim 11 , wherein
the isolation structure is not between the pad structure and the at least two through via structures within the semiconductor substrate, and
the isolation structure is not between two adjacent through via structures of the at least two through via structures within the semiconductor substrate.
13. The image sensor of claim 11 , wherein the pad structure comprises:
a pad insulation layer extending conformally on an internal wall of a pad trench extending into the semiconductor substrate from the rear surface of the semiconductor substrate; and
a pad conductive layer on the pad insulation layer, the pad conductive layer filling the pad trench.
14. The image sensor of claim 13 , wherein
the at least two through via structures are spaced apart from the pad structure in a direction parallel with the rear surface of the semiconductor substrate,
each of the at least two through via structures includes a via conductive layer on an internal wall of a through via trench, the through via trench extending through the semiconductor substrate, the via conductive layer isolated from direct contact with the pad trench, and
a portion of the pad conductive layer extends onto the rear surface of the semiconductor substrate and is connected to the via conductive layer.
15. The image sensor of claim 14 , further comprising:
a backside insulation layer on the rear surface of the semiconductor substrate,
wherein the portion of the pad conductive layer is on the backside insulation layer.
16. The image sensor of claim 13 , wherein
the at least two through via structures overlap the pad structure in the direction extending perpendicular to the rear surface of the semiconductor substrate, and
each of the at least two through via structures includes a via conductive layer on an internal wall of a through via trench, the via conductive layer connected to the pad trench, the via conductive layer connected to the pad conductive layer.
17. The image sensor of claim 11 , wherein
the pixel isolation region is on an internal wall of a pixel isolation trench,
the pixel isolation trench extends into the semiconductor substrate from the rear surface of the semiconductor substrate toward the front surface of the semiconductor substrate, and
the pixel isolation trench does not completely penetrate the semiconductor substrate.
18. The image sensor of claim 17 , wherein
the isolation structure has a sidewall inclined at a first angle with respect to the rear surface of the semiconductor substrate,
the pixel isolation region has a sidewall inclined at a second angle with respect to the rear surface of the semiconductor substrate, and the second angle is the same as the first angle.
19. The image sensor of claim 11 , wherein
the pixel isolation region is on an internal wall of a pixel isolation trench, and
the pixel isolation trench penetrates the semiconductor substrate from the front surface of the semiconductor substrate toward the rear surface of the semiconductor substrate.
20. The image sensor of claim 19 , wherein the pixel isolation region comprises:
a pixel isolation layer on the internal wall of the pixel isolation trench; and
a pixel isolation conductive layer on the pixel isolation layer, the pixel isolation conductive layer filling the pixel isolation trench.