IP Library › Granted Patent US 10,978,406
Granted Patent B2
US 10,978,406 · App. 16/007,032 · Granted Apr 13, 2021

Semiconductor package including EMI shielding structure and method for forming the same

Inventors: Hung-Jen Chang (Taoyuan, TW); Jen-Chuan Chen (Taoyuan, TW); Hsueh-Te Wang (Hsinchu, TW); Wen-Sung Hsu (Zhubei, TW)
Assignee: MediaTek Inc.
H01L23/552H01L21/32051H01L21/561H01L21/565H01L23/3121H01L23/3675H01L23/5386H01L24/97H01L25/0655H01L25/16H01L21/2855H01L21/4853H01L23/367H01L23/49805H01L23/5383H01L24/16H01L24/73H01L24/81H01L24/92H01L25/165H01L2224/16227H01L2224/32225H01L2224/73204H01L2224/92125H01L2224/97H01L2225/06537H01L2924/15159H01L2924/15162H01L2924/15192H01L2924/15311H01L2924/15313H01L2924/1815H01L2924/19041H01L2924/19042H01L2924/19043H01L2924/19105H01L2924/3025H01L2924/3511H01L2924/35121H01L2924/37001
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Quick Facts
Patent No.
US 10,978,406
App. No.
16/007,032
Granted
Apr 13, 2021
Kind
B2
Abstract

A semiconductor package structure including an encapsulating layer, a package substrate, and a conductive shielding layer is provided. The package substrate has a device region covered by the encapsulating layer and an edge region surrounding the device region and exposed from the encapsulating layer. The package substrate includes an insulating layer and a patterned conductive layer in a level of the insulating layer. The patterned conductive layer includes conductors in and along the edge region. The edge region is partially exposed from the conductors, as viewed from a top-view perspective. The conductive shielding layer covers and surrounds the encapsulating layer and is electrically connected to the conductors.

Claims (29)

1. A semiconductor package structure, comprising:

an encapsulating layer;

a package substrate having a device region covered by the encapsulating layer and an edge region surrounding the device region and exposed from the encapsulating layer, the package substrate comprising:

an insulating layer; and

a first patterned conductive layer in a first layer-level of the insulating layer, comprising a plurality of first conductors in and along the edge region to surround the device region, wherein the edge region is partially exposed from the plurality of first conductors, as viewed from a top-view perspective:

a semiconductor die disposed on the device region of the package substrate and surrounded by the encapsulating layer; and

a conductive shielding layer covering and surrounding the encapsulating layer and electrically connected to the plurality of first conductors,

wherein the conductive shielding layer covers sidewalls of the package substrate above a top surface of the plurality of first conductors,

wherein the first patterned conductive layer is on a bottom surface of the package substrate as viewed from a cross-sectional-view perspective.

2. The semiconductor package structure as claimed in claim 1 , wherein the top surface of the plurality of first conductors is in direct contact with the conductive shielding layer.

3. The semiconductor package structure as claimed in claim 1 , wherein each conductor of the plurality of first conductors is a metal via or a metal layer.

4. The semiconductor package structure as claimed in claim 1 , wherein the encapsulating layer has sidewalls that are tapered.

5. The semiconductor package structure as claimed in claim 4 , wherein portions of the conductive shielding layer that surround the sidewalls of the encapsulating layer have sidewalls aligned with sidewalls of the package substrate.

6. The semiconductor package structure as claimed in claim 1 , further comprising a heat spreader over the conductive shielding layer.

7. The semiconductor package structure of claim 1 , wherein the conductive shielding layer surrounds the package substrate.

8. A semiconductor package structure, comprising:

an encapsulating layer;

a package substrate having a device region covered by the encapsulating layer and an edge region surrounding the device region and exposed from the encapsulating layer, the package substrate comprising:

an insulating layer; and

a first patterned conductive layer in a first layer-level of the insulating layer, comprising a conductive continuous layer in and extending along the edge region to surround the device region;

a semiconductor die disposed on the device region of the package substrate and surrounded by the encapsulating layer; and

a conductive shielding layer covering and surrounding the encapsulating layer and electrically connected to the conductive continuous layer,

wherein the conductive shielding layer covers sidewalls of the package substrate above a top surface of the conductive continuous layer,

wherein the first patterned conductive layer is on a bottom surface of the package substrate as viewed from a cross-sectional-view perspective.

9. The semiconductor package structure as claimed in claim 8 , wherein the top surface of the conductive continuous layer is in direct contact with the conductive shielding layer.

10. The semiconductor package structure as claimed in claim 8 , wherein the encapsulating layer has sidewalls that are tapered.

11. The semiconductor package structure as claimed in claim 10 , wherein portions of the conductive shielding layer that surround the sidewalls of the encapsulating layer have aligned with sidewalls of the package substrate.

12. The semiconductor package structure as claimed in claim 8 , further comprising a heat spreader over the conductive shielding layer.

13. The semiconductor package structure of claim 8 , wherein the conductive shielding layer surrounds the package substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 13, 2018
From: CHANG, HUNG-JEN; CHEN, JEN-CHUAN; WANG, HSUEH-TE; HSU, WEN-SUNG
To: MEDIATEK INC.
Reel/Frame 046069/0547 →
Continuity (2)
Provisional Application 62531912 · Jul 13, 2017
Related Publication 20190019763A1 · Jan 17, 2019