IP Library › Granted Patent US 10,978,432
Granted Patent B2
US 10,978,432 · App. 16/419,782 · Granted Apr 13, 2021

Semiconductor package

Inventor: Kilsoo Kim (Hwaseong-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H01L25/105H01L21/4853H01L21/565H01L21/78H01L23/3128H01L24/73H01L25/50H01L2224/73257H01L2225/1023H01L2225/1041H01L2225/1058H01L2924/19105
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Quick Facts
Patent No.
US 10,978,432
App. No.
16/419,782
Granted
Apr 13, 2021
Kind
B2
Abstract

A semiconductor package includes a first semiconductor package, a second semiconductor package on the first semiconductor package, and a plurality of connection terminals between the first semiconductor package and the second semiconductor package. The first semiconductor package may include a package substrate, a semiconductor chip on the package substrate and having a first surface and a second surface facing each other, the first surface being adjacent to the second semiconductor package, a plurality of connection pads between the first surface of the semiconductor chip and the connection terminals, and a molding layer on the package substrate and covering side surfaces of the semiconductor chip, the molding layer being spaced apart from the connection terminals.

Claims (63)

1. A semiconductor package, comprising:

a first semiconductor package;

a second semiconductor package on the first semiconductor package; and

a plurality of connection terminals between the first semiconductor package and the second semiconductor package, wherein:

the first semiconductor package includes:

a package substrate;

a semiconductor chip on the package substrate and having a first surface and a second surface facing each other, the first surface being adjacent to the second semiconductor package;

a plurality of connection pads between the first surface of the semiconductor chip and the connection terminals; and

a molding layer on the package substrate and covering side surfaces of the semiconductor chip, the molding layer being spaced apart from the connection terminals, and

the semiconductor chip includes:

a first part on which the connection pads are disposed; and

a second part between the first part and a side surface of the semiconductor chip, the second part of the semiconductor chip being recessed from the first surface of the first part of the semiconductor chip.

2. The semiconductor package as claimed in claim 1 , wherein the first semiconductor package further includes a plurality of chip terminals between the package substrate and the second surface of the semiconductor chip.

3. The semiconductor package as claimed in claim 1 , wherein the first semiconductor package further includes a plurality of bonding wires between the package substrate and the first surface of the semiconductor chip, the bonding wires being disposed on the second part of the semiconductor chip.

4. The semiconductor package as claimed in claim 1 , wherein the first semiconductor package further includes a plurality of bonding wires between the package substrate and the first surface of the semiconductor chip, the molding layer covering the bonding wires.

5. The semiconductor package as claimed in claim 1 , wherein the connection terminals are in contact with the connection pads.

6. The semiconductor package as claimed in claim 1 , wherein the first semiconductor package further includes:

a plurality of bonding wires between the package substrate and the first surface of the semiconductor chip; and

a plurality of connection patterns on the first surface of the semiconductor chip and connecting the connection pads to the bonding wires.

7. The semiconductor package as claimed in claim 1 , wherein the first semiconductor package further includes a passive device on the package substrate.

8. The semiconductor package as claimed in claim 1 , wherein the first semiconductor package further includes an insulation layer on the first surface of the semiconductor chip, the insulation layer exposing the connection pads, a top surface of the molding layer being coplanar with a top surface of the insulation layer.

9. The semiconductor package as claimed in claim 1 , wherein the first semiconductor package further includes an insulation layer on the first surface of the semiconductor chip, the insulation layer exposing the connection pads, a top surface of the molding layer being located at a level higher than that of a top surface of the insulation layer.

10. The semiconductor package as claimed in claim 1 , wherein the second semiconductor package has a width the same as or less than a width of the first semiconductor package.

11. The semiconductor package as claimed in claim 1 , wherein:

the first surface of the semiconductor chip is an inactive surface, and

the second surface of the semiconductor chip is an active surface.

12. A semiconductor package, comprising:

a first semiconductor package;

a second semiconductor package on the first semiconductor package; and

a plurality of connection terminals between the first semiconductor package and the second semiconductor package, wherein:

the first semiconductor package includes:

a package substrate;

a semiconductor chip on the package substrate and having a first surface and a second surface facing each other;

a plurality of chip terminals between the package substrate and the second surface of the semiconductor chip; and

a plurality of connection pads between the first surface of the semiconductor chip and the connection terminals, and

the semiconductor chip includes:

a first part on which the connection pads are disposed; and

a second part between the first part and a side surface of the semiconductor chip, the second part of the semiconductor chip being recessed from the first surface of the first part of the semiconductor chip.

13. The semiconductor package as claimed in claim 12 , wherein the connection pads are spaced apart from each other in a first direction and a second direction intersecting each other.

14. The semiconductor package as claimed in claim 12 , wherein the first semiconductor package further includes a molding layer on the package substrate and covering side surfaces of the semiconductor chip, the molding layer being spaced apart from the connection terminals.

15. The semiconductor package as claimed in claim 12 , wherein the first semiconductor package further includes a plurality of bonding wires between the package substrate and the first surface of the semiconductor chip, the bonding wires being disposed on the second part of the semiconductor chip.

16. The semiconductor package as claimed in claim 12 , wherein:

the first semiconductor package further includes a molding layer that covers side surfaces of the semiconductor chips,

the molding layer does not overlap the first part, and

the molding layer overlaps the second part.

17. The semiconductor package as claimed in claim 12 , wherein the first semiconductor package further includes a plurality of connection patterns on the first surface of the semiconductor chip, the connection patterns being disposed to correspond to the connection pads.

18. The semiconductor package as claimed in claim 12 , wherein the first semiconductor package further includes:

a molding layer that covers side surfaces of the semiconductor chip; and

an insulation layer on the first surface of the semiconductor chip and exposing the connection pads, a top surface of the molding layer being coplanar with a top surface of the insulation layer.

19. The semiconductor package as claimed in claim 12 , wherein

the first surface of the semiconductor chip is an inactive surface, and

the second surface of the semiconductor chip is an active surface.

20. A semiconductor package, comprising:

a first semiconductor package;

a second semiconductor package on the first semiconductor package; and

a plurality of connection terminals between the first semiconductor package and the second semiconductor package, wherein:

the first semiconductor package includes:

a package substrate;

a semiconductor chip on the package substrate and having a first surface and a second surface facing each other, the first surface being adjacent to the second semiconductor package;

a plurality of connection pads between the first surface of the semiconductor chip and the connection terminals;

a molding layer on the package substrate and covering side surfaces of the semiconductor chip, the molding layer being spaced apart from the connection terminals;

a plurality of bonding wires between the package substrate and the first surface of the semiconductor chip; and

a plurality of connection patterns on the first surface of the semiconductor chip and connecting the connection pads to the bonding wires.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2019
From: KIM, KILSOO
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 049257/0778 →
Priority Claims (1)
KR 10-2018-0066715 · Jun 11, 2018 · national
Continuity (1)
Related Publication 20190378826A1 · Dec 12, 2019
Cited By (2)
US 12,406,917 US 12,733,548